clocksource/drivers/fttmr010: Use state container
This converts the Faraday FTTMR010 to use the state container design pattern. Take some care to handle the state container and free:ing of resources as has been done in the Moxa driver. Cc: Joel Stanley <joel@jms.id.au> Tested-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>hifive-unleashed-5.1
Linus Walleij
Daniel Lezcano
parent
dd98442e17
commit
e7bad212ca
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@ -15,6 +15,7 @@
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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/*
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* Register definitions for the timers
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@ -62,23 +63,35 @@
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#define TIMER_3_INT_OVERFLOW (1 << 8)
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#define TIMER_INT_ALL_MASK 0x1ff
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static unsigned int tick_rate;
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static void __iomem *base;
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struct fttmr010 {
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void __iomem *base;
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unsigned int tick_rate;
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struct clock_event_device clkevt;
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};
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/* A local singleton used by sched_clock, which is stateless */
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static struct fttmr010 *local_fttmr;
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static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
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{
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return container_of(evt, struct fttmr010, clkevt);
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}
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static u64 notrace fttmr010_read_sched_clock(void)
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{
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return readl(base + TIMER3_COUNT);
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return readl(local_fttmr->base + TIMER3_COUNT);
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}
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static int fttmr010_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct fttmr010 *fttmr010 = to_fttmr010(evt);
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u32 cr;
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/* Setup the match register */
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cr = readl(base + TIMER1_COUNT);
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writel(cr + cycles, base + TIMER1_MATCH1);
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if (readl(base + TIMER1_COUNT) - cr > cycles)
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cr = readl(fttmr010->base + TIMER1_COUNT);
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writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
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if (readl(fttmr010->base + TIMER1_COUNT) - cr > cycles)
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return -ETIME;
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return 0;
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@ -86,99 +99,90 @@ static int fttmr010_timer_set_next_event(unsigned long cycles,
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static int fttmr010_timer_shutdown(struct clock_event_device *evt)
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{
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struct fttmr010 *fttmr010 = to_fttmr010(evt);
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u32 cr;
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/*
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* Disable also for oneshot: the set_next() call will arm the timer
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* instead.
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*/
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/* Stop timer and interrupt. */
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cr = readl(base + TIMER_CR);
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cr = readl(fttmr010->base + TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, base + TIMER_CR);
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writel(cr, fttmr010->base + TIMER_CR);
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return 0;
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}
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static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
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{
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struct fttmr010 *fttmr010 = to_fttmr010(evt);
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u32 cr;
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/* Stop timer and interrupt. */
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cr = readl(fttmr010->base + TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, fttmr010->base + TIMER_CR);
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/* Setup counter start from 0 */
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writel(0, base + TIMER1_COUNT);
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writel(0, base + TIMER1_LOAD);
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writel(0, fttmr010->base + TIMER1_COUNT);
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writel(0, fttmr010->base + TIMER1_LOAD);
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/* enable interrupt */
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cr = readl(base + TIMER_INTR_MASK);
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/* Enable interrupt */
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cr = readl(fttmr010->base + TIMER_INTR_MASK);
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cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
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cr |= TIMER_1_INT_MATCH1;
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writel(cr, base + TIMER_INTR_MASK);
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writel(cr, fttmr010->base + TIMER_INTR_MASK);
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/* start the timer */
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cr = readl(base + TIMER_CR);
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/* Start the timer */
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cr = readl(fttmr010->base + TIMER_CR);
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cr |= TIMER_1_CR_ENABLE;
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writel(cr, base + TIMER_CR);
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writel(cr, fttmr010->base + TIMER_CR);
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return 0;
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}
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static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
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{
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u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
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struct fttmr010 *fttmr010 = to_fttmr010(evt);
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u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
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u32 cr;
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/* Stop timer and interrupt */
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cr = readl(base + TIMER_CR);
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cr = readl(fttmr010->base + TIMER_CR);
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cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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writel(cr, base + TIMER_CR);
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writel(cr, fttmr010->base + TIMER_CR);
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/* Setup timer to fire at 1/HT intervals. */
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cr = 0xffffffff - (period - 1);
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writel(cr, base + TIMER1_COUNT);
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writel(cr, base + TIMER1_LOAD);
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writel(cr, fttmr010->base + TIMER1_COUNT);
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writel(cr, fttmr010->base + TIMER1_LOAD);
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/* enable interrupt on overflow */
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cr = readl(base + TIMER_INTR_MASK);
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cr = readl(fttmr010->base + TIMER_INTR_MASK);
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cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
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cr |= TIMER_1_INT_OVERFLOW;
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writel(cr, base + TIMER_INTR_MASK);
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writel(cr, fttmr010->base + TIMER_INTR_MASK);
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/* Start the timer */
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cr = readl(base + TIMER_CR);
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cr = readl(fttmr010->base + TIMER_CR);
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cr |= TIMER_1_CR_ENABLE;
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cr |= TIMER_1_CR_INT;
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writel(cr, base + TIMER_CR);
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writel(cr, fttmr010->base + TIMER_CR);
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return 0;
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}
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/* Use TIMER1 as clock event */
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static struct clock_event_device fttmr010_clockevent = {
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.name = "TIMER1",
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/* Reasonably fast and accurate clock event */
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.rating = 300,
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = fttmr010_timer_set_next_event,
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.set_state_shutdown = fttmr010_timer_shutdown,
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.set_state_periodic = fttmr010_timer_set_periodic,
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.set_state_oneshot = fttmr010_timer_shutdown,
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.tick_resume = fttmr010_timer_shutdown,
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};
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &fttmr010_clockevent;
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction fttmr010_timer_irq = {
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.name = "Faraday FTTMR010 Timer Tick",
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.flags = IRQF_TIMER,
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.handler = fttmr010_timer_interrupt,
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};
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static int __init fttmr010_timer_init(struct device_node *np)
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{
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struct fttmr010 *fttmr010;
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int irq;
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struct clk *clk;
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int ret;
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@ -198,53 +202,91 @@ static int __init fttmr010_timer_init(struct device_node *np)
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pr_err("failed to enable PCLK\n");
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return ret;
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}
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tick_rate = clk_get_rate(clk);
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base = of_iomap(np, 0);
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if (!base) {
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fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
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if (!fttmr010) {
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ret = -ENOMEM;
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goto out_disable_clock;
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}
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fttmr010->tick_rate = clk_get_rate(clk);
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fttmr010->base = of_iomap(np, 0);
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if (!fttmr010->base) {
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pr_err("Can't remap registers");
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return -ENXIO;
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ret = -ENXIO;
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goto out_free;
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}
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/* IRQ for timer 1 */
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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return -EINVAL;
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ret = -EINVAL;
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goto out_unmap;
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}
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/*
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* Reset the interrupt mask and status
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*/
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writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK);
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writel(0, base + TIMER_INTR_STATE);
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writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR);
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writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
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writel(0, fttmr010->base + TIMER_INTR_STATE);
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writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled.)
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*/
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writel(0, base + TIMER3_COUNT);
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writel(0, base + TIMER3_LOAD);
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writel(0, base + TIMER3_MATCH1);
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writel(0, base + TIMER3_MATCH2);
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clocksource_mmio_init(base + TIMER3_COUNT,
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"fttmr010_clocksource", tick_rate,
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local_fttmr = fttmr010;
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writel(0, fttmr010->base + TIMER3_COUNT);
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writel(0, fttmr010->base + TIMER3_LOAD);
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writel(0, fttmr010->base + TIMER3_MATCH1);
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writel(0, fttmr010->base + TIMER3_MATCH2);
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clocksource_mmio_init(fttmr010->base + TIMER3_COUNT,
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"FTTMR010-TIMER3",
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fttmr010->tick_rate,
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300, 32, clocksource_mmio_readl_up);
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sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate);
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sched_clock_register(fttmr010_read_sched_clock, 32,
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fttmr010->tick_rate);
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/*
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* Setup clockevent timer (interrupt-driven.)
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* Setup clockevent timer (interrupt-driven) on timer 1.
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*/
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writel(0, base + TIMER1_COUNT);
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writel(0, base + TIMER1_LOAD);
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writel(0, base + TIMER1_MATCH1);
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writel(0, base + TIMER1_MATCH2);
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setup_irq(irq, &fttmr010_timer_irq);
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fttmr010_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&fttmr010_clockevent, tick_rate,
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writel(0, fttmr010->base + TIMER1_COUNT);
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writel(0, fttmr010->base + TIMER1_LOAD);
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writel(0, fttmr010->base + TIMER1_MATCH1);
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writel(0, fttmr010->base + TIMER1_MATCH2);
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ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
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"FTTMR010-TIMER1", &fttmr010->clkevt);
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if (ret) {
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pr_err("FTTMR010-TIMER1 no IRQ\n");
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goto out_unmap;
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}
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fttmr010->clkevt.name = "FTTMR010-TIMER1";
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/* Reasonably fast and accurate clock event */
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fttmr010->clkevt.rating = 300;
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fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT;
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fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
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fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
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fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
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fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
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fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
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fttmr010->clkevt.cpumask = cpumask_of(0);
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fttmr010->clkevt.irq = irq;
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clockevents_config_and_register(&fttmr010->clkevt,
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fttmr010->tick_rate,
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1, 0xffffffff);
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return 0;
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out_unmap:
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iounmap(fttmr010->base);
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out_free:
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kfree(fttmr010);
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out_disable_clock:
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clk_disable_unprepare(clk);
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return ret;
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}
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CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
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CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
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