Devicetree fixes for 5.2:
- Update checkpatch.pl to use DT vendor-prefixes.yaml - Fix DT binding references to files converted to DT schema - Clean-up Arm CPU binding examples to match schema - Add Sifive block versioning scheme documentation - Pass binding directory base to validation tools for reference lookups -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAlzoTXoQHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhw2sBD/9GN9RJWPlNhfwEtQrkv8RplcKUaSWdT9m1 HrHDeU8IkKVFbjIv44qq6fGmoPJSGJf87kmPh38n42IvrL17dB+QaUKBOYqGzvLU GXAwYVOAFSnW/Xt72dQz/8M9rnf9hd8uTTjlknZ0ssUwMHkORRUrQDUvhgrcdP+g 1sBJRrqgJhHtCtooeXZsDwK0J+Asw2PQA9dBgP+anROvVr7hR9w0dFyOW1cNeZo7 l1Eu8RRAH3yyOooCGM1B+Vy/9xmytBx1pHQm5EwOxptRVxZbHrSEZvO7pG5EMCb5 K+nUz7CaKgdNVF2bzOkkjpVrF3+qA+zhmSAji5sxDRsx5nhq1OuZKfqMW+6V4cyJ lolBXQC/9IaFckZOrctlIfuB/slCxwmkO9frZ4Uv6co1fHCdAmq8FbU7ooEsKE40 uKAnr6TkkadkdLkkr8cW7DdEk769LA5Y4LMeUzxgEGz3dOz0C7GyU7wnMKCr2zep Xs5KccNVXWZfxV4hFsNncqgSJi02ogRtORr7zzcD7Z/eoBT6ATNsCq1BMDzcdQbd cPJ61521HUrO0PB0m92gPTLrUcF+PilFE8O19tlzM749gUDiKosuHgWTvEmmmHA6 lX1+d2cNWX+usnYfNtu+R7WufwGvXceoPje/LICxG74LEwXDZYBasl5tqhrt6V/J EN+rL8jMZQ== =7oNi -----END PGP SIGNATURE----- Merge tag 'devicetree-fixes-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree fixes from Rob Herring: - Update checkpatch.pl to use DT vendor-prefixes.yaml - Fix DT binding references to files converted to DT schema - Clean-up Arm CPU binding examples to match schema - Add Sifive block versioning scheme documentation - Pass binding directory base to validation tools for reference lookups * tag 'devicetree-fixes-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: checkpatch.pl: Update DT vendor prefix check dt: bindings: mtd: replace references to nand.txt with nand-controller.yaml dt-bindings: interrupt-controller: arm,gic: Fix schema errors in example dt-bindings: arm: Clean up CPU binding examples dt: fix refs that were renamed to json with the same file name dt-bindings: Pass binding directory to validation tools dt-bindings: sifive: describe sifive-blocks versioninghifive-unleashed-5.2
Linus Torvalds
commit
e7bd3e248b
|
|
@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
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DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
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||||
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quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
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cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \
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cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
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$(DT_EXTRACT_EX) $< > $@
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$(obj)/%.example.dts: $(src)/%.yaml FORCE
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|
|
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|
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@ -216,7 +216,7 @@ Example:
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#size-cells = <0>;
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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@ -225,7 +225,7 @@ Example:
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.....
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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@ -118,7 +118,7 @@ cpus {
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};
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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@ -129,7 +129,7 @@ cpus {
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};
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A57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
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@ -140,7 +140,7 @@ cpus {
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};
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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@ -151,7 +151,7 @@ cpus {
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};
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A53_1: cpu@101 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x101>;
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device_type = "cpu";
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enable-method = "psci";
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@ -162,7 +162,7 @@ cpus {
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};
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A53_2: cpu@102 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x102>;
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device_type = "cpu";
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enable-method = "psci";
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@ -173,7 +173,7 @@ cpus {
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};
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A53_3: cpu@103 {
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compatible = "arm,cortex-a53","arm,armv8";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
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@ -41,7 +41,7 @@ Examples:
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Consumer:
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========
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See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
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Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
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Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
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further details.
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An interrupt consumer on an SoC using crossbar will use:
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@ -35,7 +35,7 @@ board device tree, including the system base clock, as selected by XOM[0]
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pin of the SoC. Refer to generic fixed rate clock bindings
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documentation[1] for more information how to specify these clocks.
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[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
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[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
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Example: Clock controller node:
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@ -92,6 +92,8 @@ properties:
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minItems: 2
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maxItems: 4
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ranges: true
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interrupts:
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description: Interrupt source of the parent interrupt controller on
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secondary GICs, or VGIC maintenance interrupt on primary GIC (see
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@ -197,28 +199,28 @@ examples:
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interrupt-controller@e1101000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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interrupts = <1 8 0xf04>;
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ranges = <0 0 0 0xe1100000 0 0x100000>;
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reg = <0x0 0xe1110000 0 0x01000>,
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<0x0 0xe112f000 0 0x02000>,
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<0x0 0xe1140000 0 0x10000>,
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<0x0 0xe1160000 0 0x10000>;
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ranges = <0 0xe1100000 0x100000>;
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reg = <0xe1110000 0x01000>,
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<0xe112f000 0x02000>,
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<0xe1140000 0x10000>,
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<0xe1160000 0x10000>;
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v2m0: v2m@8000 {
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v2m0: v2m@80000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x80000 0 0x1000>;
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reg = <0x80000 0x1000>;
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};
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//...
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v2mN: v2m@9000 {
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v2mN: v2m@90000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x90000 0 0x1000>;
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reg = <0x90000 0x1000>;
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};
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};
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...
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@ -23,7 +23,7 @@ Required properties:
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- marvell,spi-base : List of GIC base SPI interrupts, one for each
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ODMI frame. Those SPI interrupts are 0-based,
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i.e marvell,spi-base = <128> will use SPI #96.
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See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
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See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
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for details about the GIC Device Tree binding.
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Example:
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@ -15,7 +15,7 @@ Optional properties:
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- power-supply: specifies the power source. It can either be a regulator
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or a gpio which enables a regulator, i.e. a regulator-fixed as
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described in
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Documentation/devicetree/bindings/regulator/fixed-regulator.txt
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Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
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Example:
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@ -24,7 +24,7 @@ Optional children nodes:
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Children nodes represent the available nand chips.
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Other properties:
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see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
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see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
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Example demonstrate on AXG SoC:
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@ -101,12 +101,12 @@ Required properties:
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number (e.g., 0, 1, 2, etc.)
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- #address-cells : see partition.txt
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- #size-cells : see partition.txt
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- nand-ecc-strength : see nand.txt
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- nand-ecc-step-size : must be 512 or 1024. See nand.txt
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- nand-ecc-strength : see nand-controller.yaml
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- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
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Optional properties:
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- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
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chip-select. See nand.txt
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chip-select. See nand-controller.yaml
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- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
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expected for the ECC layout in use. This size, in
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addition to the strength and step-size,
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@ -22,16 +22,16 @@ Sub-nodes:
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select is connected.
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Optional properties:
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- nand-ecc-step-size: see nand.txt for details.
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- nand-ecc-step-size: see nand-controller.yaml for details.
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If present, the value must be
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512 for "altr,socfpga-denali-nand"
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1024 for "socionext,uniphier-denali-nand-v5a"
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1024 for "socionext,uniphier-denali-nand-v5b"
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- nand-ecc-strength: see nand.txt for details. Valid values are:
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- nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
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8, 15 for "altr,socfpga-denali-nand"
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8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
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8, 16 for "socionext,uniphier-denali-nand-v5b"
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- nand-ecc-maximize: see nand.txt for details
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- nand-ecc-maximize: see nand-controller.yaml for details
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The chip nodes may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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@ -30,9 +30,9 @@ Optional properties:
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command is asserted. Zero means one cycle, 255 means 256
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cycles.
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- bank: default NAND bank to use (0-3 are valid, 0 is the default).
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- nand-ecc-mode : see nand.txt
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- nand-ecc-strength : see nand.txt
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- nand-ecc-step-size : see nand.txt
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- nand-ecc-mode : see nand-controller.yaml
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- nand-ecc-strength : see nand-controller.yaml
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- nand-ecc-step-size : see nand-controller.yaml
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Can support 1-bit HW ECC (default) or if stronger correction is required,
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software-based BCH.
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@ -8,7 +8,7 @@ explained in a separate documents - please refer to
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Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
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For NAND specific properties such as ECC modes or bus width, please refer to
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Documentation/devicetree/bindings/mtd/nand.txt
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Documentation/devicetree/bindings/mtd/nand-controller.yaml
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Required properties:
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|
|
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@ -7,7 +7,7 @@ Required properties:
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NAND controller's registers. The second contains base
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physical address and size of NAND controller's buffer.
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- interrupts: Interrupt number for nfc.
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- nand-bus-width: See nand.txt.
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- nand-bus-width: See nand-controller.yaml.
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- nand-ecc-mode: Support none and hw ecc mode.
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- #address-cells: Partition address, should be set 1.
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- #size-cells: Partition size, should be set 1.
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|
|
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@ -36,29 +36,29 @@ Children nodes represent the available NAND chips.
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Required properties:
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- reg: shall contain the native Chip Select ids (0-3).
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- nand-rb: see nand.txt (0-1).
|
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- nand-rb: see nand-controller.yaml (0-1).
|
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Optional properties:
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- marvell,nand-keep-config: orders the driver not to take the timings
|
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from the core and leaving them completely untouched. Bootloader
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timings will then be used.
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- label: MTD name.
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- nand-on-flash-bbt: see nand.txt.
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- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
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- nand-ecc-algo: see nand.txt. This property is essentially useful when
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- nand-on-flash-bbt: see nand-controller.yaml.
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- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
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- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
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not using hardware ECC. Howerver, it may be added when using hardware
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ECC for clarification but will be ignored by the driver because ECC
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mode is chosen depending on the page size and the strength required by
|
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the NAND chip. This value may be overwritten with nand-ecc-strength
|
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property.
|
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- nand-ecc-strength: see nand.txt.
|
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- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
|
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- nand-ecc-strength: see nand-controller.yaml.
|
||||
- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
|
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use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
|
||||
step size will shrink or grow in order to fit the required strength.
|
||||
Step sizes are not completely random for all and follow certain
|
||||
patterns described in AN-379, "Marvell SoC NFC ECC".
|
||||
|
||||
See Documentation/devicetree/bindings/mtd/nand.txt for more details on
|
||||
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
|
||||
generic bindings.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ Required properties:
|
|||
- compatible: "fsl,imxXX-nand"
|
||||
- reg: address range of the nfc block
|
||||
- interrupts: irq to be used
|
||||
- nand-bus-width: see nand.txt
|
||||
- nand-ecc-mode: see nand.txt
|
||||
- nand-on-flash-bbt: see nand.txt
|
||||
- nand-bus-width: see nand-controller.yaml
|
||||
- nand-ecc-mode: see nand-controller.yaml
|
||||
- nand-on-flash-bbt: see nand-controller.yaml
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -26,14 +26,14 @@ Optional children node properties:
|
|||
"hw" is supported.
|
||||
- nand-ecc-algo: string, algorithm of NAND ECC.
|
||||
Supported values with "hw" ECC mode are: "rs", "bch".
|
||||
- nand-bus-width : See nand.txt
|
||||
- nand-on-flash-bbt: See nand.txt
|
||||
- nand-bus-width : See nand-controller.yaml
|
||||
- nand-on-flash-bbt: See nand-controller.yaml
|
||||
- nand-ecc-strength: integer representing the number of bits to correct
|
||||
per ECC step (always 512). Supported strength using HW ECC
|
||||
modes are:
|
||||
- RS: 4, 6, 8
|
||||
- BCH: 4, 8, 14, 16
|
||||
- nand-ecc-maximize: See nand.txt
|
||||
- nand-ecc-maximize: See nand-controller.yaml
|
||||
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
|
||||
are chosen.
|
||||
- wp-gpios: GPIO specifier for the write protect pin.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
* Oxford Semiconductor OXNAS NAND Controller
|
||||
|
||||
Please refer to nand.txt for generic information regarding MTD NAND bindings.
|
||||
Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "oxsemi,ox820-nand"
|
||||
|
|
|
|||
|
|
@ -47,8 +47,8 @@ Required properties:
|
|||
- #size-cells: see partition.txt
|
||||
|
||||
Optional properties:
|
||||
- nand-bus-width: see nand.txt
|
||||
- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will
|
||||
- nand-bus-width: see nand-controller.yaml
|
||||
- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
|
||||
be used according to chip requirement and available
|
||||
OOB size.
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ Required properties:
|
|||
"samsung,s3c2412-nand"
|
||||
"samsung,s3c2440-nand"
|
||||
- reg : register's location and length.
|
||||
- #address-cells, #size-cells : see nand.txt
|
||||
- #address-cells, #size-cells : see nand-controller.yaml
|
||||
- clocks : phandle to the nand controller clock
|
||||
- clock-names : must contain "nand"
|
||||
|
||||
|
|
@ -14,8 +14,8 @@ Optional child nodes:
|
|||
Child nodes representing the available nand chips.
|
||||
|
||||
Optional child properties:
|
||||
- nand-ecc-mode : see nand.txt
|
||||
- nand-on-flash-bbt : see nand.txt
|
||||
- nand-ecc-mode : see nand-controller.yaml
|
||||
- nand-on-flash-bbt : see nand-controller.yaml
|
||||
|
||||
Each child device node may optionally contain a 'partitions' sub-node,
|
||||
which further contains sub-nodes describing the flash partition mapping.
|
||||
|
|
|
|||
|
|
@ -24,9 +24,9 @@ Required properties:
|
|||
- reg: describes the CS lines assigned to the NAND device.
|
||||
|
||||
Optional properties:
|
||||
- nand-on-flash-bbt: see nand.txt
|
||||
- nand-ecc-strength: see nand.txt
|
||||
- nand-ecc-step-size: see nand.txt
|
||||
- nand-on-flash-bbt: see nand-controller.yaml
|
||||
- nand-ecc-strength: see nand-controller.yaml
|
||||
- nand-ecc-step-size: see nand-controller.yaml
|
||||
|
||||
The following ECC strength and step size are currently supported:
|
||||
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ Required properties:
|
|||
- #size-cells: <0>
|
||||
|
||||
Children nodes represent the available NAND chips.
|
||||
See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
|
||||
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -25,14 +25,14 @@ only handle one NAND chip.
|
|||
|
||||
Required properties:
|
||||
- compatible: Should be set to "fsl,vf610-nfc-cs".
|
||||
- nand-bus-width: see nand.txt
|
||||
- nand-ecc-mode: see nand.txt
|
||||
- nand-bus-width: see nand-controller.yaml
|
||||
- nand-ecc-mode: see nand-controller.yaml
|
||||
|
||||
Required properties for hardware ECC:
|
||||
- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt)
|
||||
- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
|
||||
- nand-ecc-step-size: step size equals page size, currently only 2k pages are
|
||||
supported
|
||||
- nand-on-flash-bbt: see nand.txt
|
||||
- nand-on-flash-bbt: see nand-controller.yaml
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
DT compatible string versioning for SiFive open-source IP blocks
|
||||
|
||||
This document describes the version specification for DT "compatible"
|
||||
strings for open-source SiFive IP blocks. HDL for these IP blocks
|
||||
can be found in this public repository:
|
||||
|
||||
https://github.com/sifive/sifive-blocks
|
||||
|
||||
IP block-specific DT compatible strings are contained within the HDL,
|
||||
in the form "sifive,<ip-block-name><integer version number>".
|
||||
|
||||
An example is "sifive,uart0" from:
|
||||
|
||||
https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
|
||||
|
||||
Until these IP blocks (or IP integration) support version
|
||||
auto-discovery, the maintainers of these IP blocks intend to increment
|
||||
the suffixed number in the compatible string whenever the software
|
||||
interface to these IP blocks changes, or when the functionality of the
|
||||
underlying IP blocks changes in a way that software should be aware of.
|
||||
|
||||
Driver developers can use compatible string "match" values such as
|
||||
"sifive,uart0" to indicate that their driver is compatible with the
|
||||
register interface and functionality associated with the relevant
|
||||
upstream sifive-blocks commits. It is expected that most drivers will
|
||||
match on these IP block-specific compatible strings.
|
||||
|
||||
DT data authors, when writing data for a particular SoC, should
|
||||
continue to specify an SoC-specific compatible string value, such as
|
||||
"sifive,fu540-c000-uart". This way, if SoC-specific
|
||||
integration-specific bug fixes or workarounds are needed, the kernel
|
||||
or other system software can match on this string to apply them. The
|
||||
IP block-specific compatible string (such as "sifive,uart0") should
|
||||
then be specified as a subsequent value.
|
||||
|
||||
An example of this style:
|
||||
|
||||
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
|
||||
|
|
@ -2768,7 +2768,7 @@ AVIA HX711 ANALOG DIGITAL CONVERTER IIO DRIVER
|
|||
M: Andreas Klinger <ak@it-klinger.de>
|
||||
L: linux-iio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
|
||||
F: Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
|
||||
F: drivers/iio/adc/hx711.c
|
||||
|
||||
AX.25 NETWORK LAYER
|
||||
|
|
@ -14351,7 +14351,7 @@ SIMPLEFB FB DRIVER
|
|||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
L: linux-fbdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/simple-framebuffer.txt
|
||||
F: Documentation/devicetree/bindings/display/simple-framebuffer.yaml
|
||||
F: drivers/video/fbdev/simplefb.c
|
||||
F: include/linux/platform_data/simplefb.h
|
||||
|
||||
|
|
|
|||
|
|
@ -298,7 +298,7 @@ DT_BINDING_DIR := Documentation/devicetree/bindings
|
|||
DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/processed-schema.yaml
|
||||
|
||||
quiet_cmd_dtb_check = CHECK $@
|
||||
cmd_dtb_check = $(DT_CHECKER) -p $(DT_TMP_SCHEMA) $@ ;
|
||||
cmd_dtb_check = $(DT_CHECKER) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ ;
|
||||
|
||||
define rule_dtc_dt_yaml
|
||||
$(call cmd_and_fixdep,dtc,yaml)
|
||||
|
|
|
|||
|
|
@ -3027,7 +3027,7 @@ sub process {
|
|||
my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
|
||||
|
||||
my $dt_path = $root . "/Documentation/devicetree/bindings/";
|
||||
my $vp_file = $dt_path . "vendor-prefixes.txt";
|
||||
my $vp_file = $dt_path . "vendor-prefixes.yaml";
|
||||
|
||||
foreach my $compat (@compats) {
|
||||
my $compat2 = $compat;
|
||||
|
|
@ -3042,7 +3042,7 @@ sub process {
|
|||
|
||||
next if $compat !~ /^([a-zA-Z0-9\-]+)\,/;
|
||||
my $vendor = $1;
|
||||
`grep -Eq "^$vendor\\b" $vp_file`;
|
||||
`grep -Eq "\\"\\^\Q$vendor\E,\\.\\*\\":" $vp_file`;
|
||||
if ( $? >> 8 ) {
|
||||
WARN("UNDOCUMENTED_DT_STRING",
|
||||
"DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr);
|
||||
|
|
|
|||
Loading…
Reference in New Issue