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sh: Convert Dreamcast support from hw_interrupt_type to irq_chip

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Switch the dreamcast IRQ code over to the irq_chip way of doing things,
so that we can set GENERIC_HARDIRQS_NO__DO_IRQ for all SuperH boards.

Also, whilst I'm here change some things to make checkpatch.pl happy:
	- Indent with tabs, not with spaces
	- Include <linux/io.h>, not <asm/io.h>
	- Fix the multi-line comment style
	- Fix some typos in the comments

Tested-by: Adrian McMenamin <adrian@newgolddream.dyndns.info>
Signed-off-by: Matt Fleming <mjf@gentoo.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Matt Fleming 2008-12-14 12:02:26 +00:00 committed by Paul Mundt
parent bd0a22d21f
commit e85a47744b
2 changed files with 87 additions and 102 deletions
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184
arch/sh/boards/mach-dreamcast/irq.c
View file

@ -10,106 +10,90 @@
*/ */
#include <linux/irq.h> #include <linux/irq.h>
#include <asm/io.h> #include <linux/io.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <mach/sysasic.h> #include <mach/sysasic.h>
/* Dreamcast System ASIC Hardware Events - /*
* Dreamcast System ASIC Hardware Events -
The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving *
hardware events from system peripherals and triggering an SH7750 IRQ. * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are * hardware events from system peripherals and triggering an SH7750 IRQ.
set in the Event Mask Registers (EMRs). When a hardware event is * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
triggered, it's corresponding bit in the Event Status Registers (ESRs) * set in the Event Mask Registers (EMRs). When a hardware event is
is set, and that bit should be rewritten to the ESR to acknowledge that * triggered, its corresponding bit in the Event Status Registers (ESRs)
event. * is set, and that bit should be rewritten to the ESR to acknowledge that
* event.
There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event *
types can be found in include/asm-sh/dreamcast/sysasic.h. There are three * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event
groups of EMRs that parallel the ESRs. Each EMR group corresponds to an * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 * There are three groups of EMRs that parallel the ESRs. Each EMR group
triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
* 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
In the kernel, these events are mapped to virtual IRQs so that drivers can * triggers IRQ 9.
respond to them as they would a normal interrupt. In order to keep this *
mapping simple, the events are mapped as: * In the kernel, these events are mapped to virtual IRQs so that drivers can
* respond to them as they would a normal interrupt. In order to keep this
6900/6910 - Events 0-31, IRQ 13 * mapping simple, the events are mapped as:
6904/6924 - Events 32-63, IRQ 11 *
6908/6938 - Events 64-95, IRQ 9 * 6900/6910 - Events 0-31, IRQ 13
* 6904/6924 - Events 32-63, IRQ 11
*/ * 6908/6938 - Events 64-95, IRQ 9
*
*/
#define ESR_BASE 0x005f6900 /* Base event status register */ #define ESR_BASE 0x005f6900 /* Base event status register */
#define EMR_BASE 0x005f6910 /* Base event mask register */ #define EMR_BASE 0x005f6910 /* Base event mask register */
/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910, /*
1 = 0x6920, 2 = 0x6930; also determine the event offset */ * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
* 1 = 0x6920, 2 = 0x6930; also determine the event offset.
*/
#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
/* Return the hardware event's bit positon within the EMR/ESR */ /* Return the hardware event's bit positon within the EMR/ESR */
#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ /*
(logically mapped to the corresponding bit for the hardware event). */ * For each of these *_irq routines, the IRQ passed in is the virtual IRQ
* (logically mapped to the corresponding bit for the hardware event).
*/
/* Disable the hardware event by masking its bit in its EMR */ /* Disable the hardware event by masking its bit in its EMR */
static inline void disable_systemasic_irq(unsigned int irq) static inline void disable_systemasic_irq(unsigned int irq)
{ {
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask; __u32 mask;
mask = inl(emr); mask = inl(emr);
mask &= ~(1 << EVENT_BIT(irq)); mask &= ~(1 << EVENT_BIT(irq));
outl(mask, emr); outl(mask, emr);
} }
/* Enable the hardware event by setting its bit in its EMR */ /* Enable the hardware event by setting its bit in its EMR */
static inline void enable_systemasic_irq(unsigned int irq) static inline void enable_systemasic_irq(unsigned int irq)
{ {
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask; __u32 mask;
mask = inl(emr); mask = inl(emr);
mask |= (1 << EVENT_BIT(irq)); mask |= (1 << EVENT_BIT(irq));
outl(mask, emr); outl(mask, emr);
} }
/* Acknowledge a hardware event by writing its bit back to its ESR */ /* Acknowledge a hardware event by writing its bit back to its ESR */
static void ack_systemasic_irq(unsigned int irq) static void mask_ack_systemasic_irq(unsigned int irq)
{ {
__u32 esr = ESR_BASE + (LEVEL(irq) << 2); __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
disable_systemasic_irq(irq); disable_systemasic_irq(irq);
outl((1 << EVENT_BIT(irq)), esr); outl((1 << EVENT_BIT(irq)), esr);
} }
/* After a IRQ has been ack'd and responded to, it needs to be renabled */ struct irq_chip systemasic_int = {
static void end_systemasic_irq(unsigned int irq) .name = "System ASIC",
{ .mask = disable_systemasic_irq,
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) .mask_ack = mask_ack_systemasic_irq,
enable_systemasic_irq(irq); .unmask = enable_systemasic_irq,
}
static unsigned int startup_systemasic_irq(unsigned int irq)
{
enable_systemasic_irq(irq);
return 0;
}
static void shutdown_systemasic_irq(unsigned int irq)
{
disable_systemasic_irq(irq);
}
struct hw_interrupt_type systemasic_int = {
.typename = "System ASIC",
.startup = startup_systemasic_irq,
.shutdown = shutdown_systemasic_irq,
.enable = enable_systemasic_irq,
.disable = disable_systemasic_irq,
.ack = ack_systemasic_irq,
.end = end_systemasic_irq,
}; };
/* /*
@ -117,37 +101,37 @@ struct hw_interrupt_type systemasic_int = {
*/ */
int systemasic_irq_demux(int irq) int systemasic_irq_demux(int irq)
{ {
__u32 emr, esr, status, level; __u32 emr, esr, status, level;
__u32 j, bit; __u32 j, bit;
switch (irq) { switch (irq) {
case 13: case 13:
level = 0; level = 0;
break; break;
case 11: case 11:
level = 1; level = 1;
break; break;
case 9: case 9:
level = 2; level = 2;
break; break;
default: default:
return irq; return irq;
} }
emr = EMR_BASE + (level << 4) + (level << 2); emr = EMR_BASE + (level << 4) + (level << 2);
esr = ESR_BASE + (level << 2); esr = ESR_BASE + (level << 2);
/* Mask the ESR to filter any spurious, unwanted interrupts */ /* Mask the ESR to filter any spurious, unwanted interrupts */
status = inl(esr); status = inl(esr);
status &= inl(emr); status &= inl(emr);
/* Now scan and find the first set bit as the event to map */ /* Now scan and find the first set bit as the event to map */
for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
if (status & bit) { if (status & bit) {
irq = HW_EVENT_IRQ_BASE + j + (level << 5); irq = HW_EVENT_IRQ_BASE + j + (level << 5);
return irq; return irq;
} }
} }
/* Not reached */ /* Not reached */
return irq; return irq;
} }

5
arch/sh/boards/mach-dreamcast/setup.c
View file

@ -28,7 +28,7 @@
#include <asm/machvec.h> #include <asm/machvec.h>
#include <mach/sysasic.h> #include <mach/sysasic.h>
extern struct hw_interrupt_type systemasic_int; extern struct irq_chip systemasic_int;
extern void aica_time_init(void); extern void aica_time_init(void);
extern int gapspci_init(void); extern int gapspci_init(void);
extern int systemasic_irq_demux(int); extern int systemasic_irq_demux(int);
@ -47,7 +47,8 @@ static void __init dreamcast_setup(char **cmdline_p)
/* Assign all virtual IRQs to the System ASIC int. handler */ /* Assign all virtual IRQs to the System ASIC int. handler */
for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
irq_desc[i].chip = &systemasic_int; set_irq_chip_and_handler(i, &systemasic_int,
handle_level_irq);
board_time_init = aica_time_init; board_time_init = aica_time_init;