clk: qoriq: modify MAX_PLL_DIV to 32
On LS2088A, Watchdog need clk divided by 32, so modify MAX_PLL_DIV to 32 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -31,7 +31,7 @@
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#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
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#define CGB_PLL1 4
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#define CGB_PLL2 5
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#define MAX_PLL_DIV 16
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#define MAX_PLL_DIV 32
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struct clockgen_pll_div {
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struct clk *clk;
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