Merge branch 'linus' into perf/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>alistair/sunxi64-5.4-dsi
Ingo Molnar
commit
e98db89489
5
.mailmap
5
.mailmap
|
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@ -64,6 +64,9 @@ Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
|
|||
Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>
|
||||
Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>
|
||||
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
|
||||
Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
|
||||
Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
|
||||
Dmitry Safonov <0x7f454c46@gmail.com> <dima@arista.com>
|
||||
Domen Puncer <domen@coderock.org>
|
||||
Douglas Gilbert <dougg@torque.net>
|
||||
Ed L. Cashin <ecashin@coraid.com>
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||||
|
|
@ -160,6 +163,8 @@ Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.co
|
|||
Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
|
||||
Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
|
||||
Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
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||||
Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
|
||||
Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
|
||||
Mayuresh Janorkar <mayur@ti.com>
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||||
Michael Buesch <m@bues.ch>
|
||||
Michel Dänzer <michel@tungstengraphics.com>
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|
|
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|
|
@ -1,20 +1,30 @@
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* ARC-HS Interrupt Distribution Unit
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||||
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This optional 2nd level interrupt controller can be used in SMP configurations for
|
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dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
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This optional 2nd level interrupt controller can be used in SMP configurations
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for dynamic IRQ routing, load balancing of common/external IRQs towards core
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intc.
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Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- #interrupt-cells: Must be <1>.
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- #interrupt-cells: Must be <1> or <2>.
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Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
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of the particular interrupt line of IDU corresponds to the line N+24 of the
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core interrupt controller.
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Value of the first cell specifies the "common" IRQ from peripheral to IDU.
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Number N of the particular interrupt line of IDU corresponds to the line N+24
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of the core interrupt controller.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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The (optional) second cell specifies any of the following flags:
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- bits[3:0] trigger type and level flags
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1 = low-to-high edge triggered
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2 = NOT SUPPORTED (high-to-low edge triggered)
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4 = active high level-sensitive <<< DEFAULT
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8 = NOT SUPPORTED (active low level-sensitive)
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When no second cell is specified, the interrupt is assumed to be level
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sensitive.
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The interrupt controller is accessed via the special ARC AUX register
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interface, hence "reg" property is not specified.
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Example:
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core_intc: core-interrupt-controller {
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|
|
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20
MAINTAINERS
20
MAINTAINERS
|
|
@ -683,7 +683,7 @@ S: Maintained
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F: drivers/crypto/sunxi-ss/
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ALLWINNER VPU DRIVER
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M: Maxime Ripard <maxime.ripard@bootlin.com>
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M: Maxime Ripard <mripard@kernel.org>
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M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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L: linux-media@vger.kernel.org
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S: Maintained
|
||||
|
|
@ -1408,7 +1408,7 @@ S: Maintained
|
|||
F: drivers/clk/sunxi/
|
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|
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ARM/Allwinner sunXi SoC support
|
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M: Maxime Ripard <maxime.ripard@bootlin.com>
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M: Maxime Ripard <mripard@kernel.org>
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M: Chen-Yu Tsai <wens@csie.org>
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||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
|
@ -3577,7 +3577,7 @@ F: Documentation/filesystems/caching/cachefiles.txt
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|||
F: fs/cachefiles/
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||||
|
||||
CADENCE MIPI-CSI2 BRIDGES
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||||
M: Maxime Ripard <maxime.ripard@bootlin.com>
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||||
M: Maxime Ripard <mripard@kernel.org>
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||||
L: linux-media@vger.kernel.org
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||||
S: Maintained
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||||
F: Documentation/devicetree/bindings/media/cdns,*.txt
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||||
|
|
@ -5295,7 +5295,7 @@ F: include/linux/vga*
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|||
|
||||
DRM DRIVERS AND MISC GPU PATCHES
|
||||
M: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
|
||||
M: Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
M: Maxime Ripard <mripard@kernel.org>
|
||||
M: Sean Paul <sean@poorly.run>
|
||||
W: https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html
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||||
S: Maintained
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||||
|
|
@ -5308,7 +5308,7 @@ F: include/uapi/drm/drm*
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|||
F: include/linux/vga*
|
||||
|
||||
DRM DRIVERS FOR ALLWINNER A10
|
||||
M: Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
M: Maxime Ripard <mripard@kernel.org>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
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||||
F: drivers/gpu/drm/sun4i/
|
||||
|
|
@ -7513,7 +7513,7 @@ I2C MV64XXX MARVELL AND ALLWINNER DRIVER
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|||
M: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
|
||||
F: Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
|
||||
F: drivers/i2c/busses/i2c-mv64xxx.c
|
||||
|
||||
I2C OVER PARALLEL PORT
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|
|
@ -8454,11 +8454,6 @@ S: Maintained
|
|||
F: fs/io_uring.c
|
||||
F: include/uapi/linux/io_uring.h
|
||||
|
||||
IP MASQUERADING
|
||||
M: Juanjo Ciarlante <jjciarla@raiz.uncu.edu.ar>
|
||||
S: Maintained
|
||||
F: net/ipv4/netfilter/ipt_MASQUERADE.c
|
||||
|
||||
IPMI SUBSYSTEM
|
||||
M: Corey Minyard <minyard@acm.org>
|
||||
L: openipmi-developer@lists.sourceforge.net (moderated for non-subscribers)
|
||||
|
|
@ -11086,7 +11081,7 @@ NET_FAILOVER MODULE
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|||
M: Sridhar Samudrala <sridhar.samudrala@intel.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
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||||
F: driver/net/net_failover.c
|
||||
F: drivers/net/net_failover.c
|
||||
F: include/net/net_failover.h
|
||||
F: Documentation/networking/net_failover.rst
|
||||
|
||||
|
|
@ -14478,6 +14473,7 @@ F: drivers/net/phy/phylink.c
|
|||
F: drivers/net/phy/sfp*
|
||||
F: include/linux/phylink.h
|
||||
F: include/linux/sfp.h
|
||||
K: phylink
|
||||
|
||||
SGI GRU DRIVER
|
||||
M: Dimitri Sivanich <sivanich@sgi.com>
|
||||
|
|
|
|||
|
|
@ -12,3 +12,6 @@ dtb-y := $(builtindtb-y).dtb
|
|||
# for CONFIG_OF_ALL_DTBS test
|
||||
dtstree := $(srctree)/$(src)
|
||||
dtb- := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
|
||||
|
||||
# board-specific dtc flags
|
||||
DTC_FLAGS_hsdk += --pad 20
|
||||
|
|
|
|||
|
|
@ -256,7 +256,7 @@
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|||
|
||||
.macro FAKE_RET_FROM_EXCPN
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||||
lr r9, [status32]
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||||
bic r9, r9, (STATUS_U_MASK|STATUS_DE_MASK|STATUS_AE_MASK)
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||||
bic r9, r9, STATUS_AE_MASK
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or r9, r9, STATUS_IE_MASK
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||||
kflag r9
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||||
.endm
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||||
|
|
|
|||
|
|
@ -62,15 +62,15 @@
|
|||
#else /* !__ASSEMBLY__ */
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_ICCM
|
||||
#define __arcfp_code __attribute__((__section__(".text.arcfp")))
|
||||
#define __arcfp_code __section(.text.arcfp)
|
||||
#else
|
||||
#define __arcfp_code __attribute__((__section__(".text")))
|
||||
#define __arcfp_code __section(.text)
|
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#endif
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_DCCM
|
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#define __arcfp_data __attribute__((__section__(".data.arcfp")))
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#define __arcfp_data __section(.data.arcfp)
|
||||
#else
|
||||
#define __arcfp_data __attribute__((__section__(".data")))
|
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#define __arcfp_data __section(.data)
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
|
|||
|
|
@ -53,8 +53,7 @@ extern const struct machine_desc __arch_info_begin[], __arch_info_end[];
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|||
*/
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#define MACHINE_START(_type, _name) \
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static const struct machine_desc __mach_desc_##_type \
|
||||
__used \
|
||||
__attribute__((__section__(".arch.info.init"))) = { \
|
||||
__used __section(.arch.info.init) = { \
|
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.name = _name,
|
||||
|
||||
#define MACHINE_END \
|
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|
|
|
|||
|
|
@ -202,8 +202,8 @@ static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
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|||
__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
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}
|
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|
||||
static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
|
||||
unsigned int distr)
|
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static void idu_set_mode(unsigned int cmn_irq, bool set_lvl, unsigned int lvl,
|
||||
bool set_distr, unsigned int distr)
|
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{
|
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union {
|
||||
unsigned int word;
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||||
|
|
@ -212,8 +212,11 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
|
|||
};
|
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} data;
|
||||
|
||||
data.distr = distr;
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data.lvl = lvl;
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data.word = __mcip_cmd_read(CMD_IDU_READ_MODE, cmn_irq);
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if (set_distr)
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||||
data.distr = distr;
|
||||
if (set_lvl)
|
||||
data.lvl = lvl;
|
||||
__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
|
||||
}
|
||||
|
||||
|
|
@ -240,6 +243,25 @@ static void idu_irq_unmask(struct irq_data *data)
|
|||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
}
|
||||
|
||||
static void idu_irq_ack(struct irq_data *data)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
}
|
||||
|
||||
static void idu_irq_mask_ack(struct irq_data *data)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
|
||||
__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
}
|
||||
|
||||
static int
|
||||
idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
|
||||
bool force)
|
||||
|
|
@ -263,13 +285,36 @@ idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
|
|||
else
|
||||
distribution_mode = IDU_M_DISTRI_RR;
|
||||
|
||||
idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode);
|
||||
idu_set_mode(data->hwirq, false, 0, true, distribution_mode);
|
||||
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
|
||||
return IRQ_SET_MASK_OK;
|
||||
}
|
||||
|
||||
static int idu_irq_set_type(struct irq_data *data, u32 type)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* ARCv2 IDU HW does not support inverse polarity, so these are the
|
||||
* only interrupt types supported.
|
||||
*/
|
||||
if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_irqsave(&mcip_lock, flags);
|
||||
|
||||
idu_set_mode(data->hwirq, true,
|
||||
type & IRQ_TYPE_EDGE_RISING ? IDU_M_TRIG_EDGE :
|
||||
IDU_M_TRIG_LEVEL,
|
||||
false, 0);
|
||||
|
||||
raw_spin_unlock_irqrestore(&mcip_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void idu_irq_enable(struct irq_data *data)
|
||||
{
|
||||
/*
|
||||
|
|
@ -289,7 +334,10 @@ static struct irq_chip idu_irq_chip = {
|
|||
.name = "MCIP IDU Intc",
|
||||
.irq_mask = idu_irq_mask,
|
||||
.irq_unmask = idu_irq_unmask,
|
||||
.irq_ack = idu_irq_ack,
|
||||
.irq_mask_ack = idu_irq_mask_ack,
|
||||
.irq_enable = idu_irq_enable,
|
||||
.irq_set_type = idu_irq_set_type,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = idu_irq_set_affinity,
|
||||
#endif
|
||||
|
|
@ -317,7 +365,7 @@ static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t
|
|||
}
|
||||
|
||||
static const struct irq_domain_ops idu_irq_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.xlate = irq_domain_xlate_onetwocell,
|
||||
.map = idu_irq_map,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -572,6 +572,7 @@ static unsigned long read_pointer(const u8 **pLoc, const void *end,
|
|||
#else
|
||||
BUILD_BUG_ON(sizeof(u32) != sizeof(value));
|
||||
#endif
|
||||
/* Fall through */
|
||||
case DW_EH_PE_native:
|
||||
if (end < (const void *)(ptr.pul + 1))
|
||||
return 0;
|
||||
|
|
@ -826,7 +827,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
|
|||
case DW_CFA_def_cfa:
|
||||
state->cfa.reg = get_uleb128(&ptr.p8, end);
|
||||
unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg);
|
||||
/*nobreak*/
|
||||
/* fall through */
|
||||
case DW_CFA_def_cfa_offset:
|
||||
state->cfa.offs = get_uleb128(&ptr.p8, end);
|
||||
unw_debug("cfa_def_cfa_offset: 0x%lx ",
|
||||
|
|
@ -834,7 +835,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc,
|
|||
break;
|
||||
case DW_CFA_def_cfa_sf:
|
||||
state->cfa.reg = get_uleb128(&ptr.p8, end);
|
||||
/*nobreak */
|
||||
/* fall through */
|
||||
case DW_CFA_def_cfa_offset_sf:
|
||||
state->cfa.offs = get_sleb128(&ptr.p8, end)
|
||||
* state->dataAlign;
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
|||
if (is_isa_arcv2() && ioc_enable && coherent)
|
||||
dev->dma_coherent = true;
|
||||
|
||||
dev_info(dev, "use %sncoherent DMA ops\n",
|
||||
dev_info(dev, "use %scoherent DMA ops\n",
|
||||
dev->dma_coherent ? "" : "non");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,11 +6,15 @@
|
|||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/arcregs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach_desc.h>
|
||||
|
||||
int arc_hsdk_axi_dmac_coherent __section(.data) = 0;
|
||||
|
||||
#define ARC_CCM_UNUSED_ADDR 0x60000000
|
||||
|
||||
static void __init hsdk_init_per_cpu(unsigned int cpu)
|
||||
|
|
@ -97,6 +101,42 @@ static void __init hsdk_enable_gpio_intc_wire(void)
|
|||
iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
|
||||
}
|
||||
|
||||
static int __init hsdk_tweak_node_coherency(const char *path, bool coherent)
|
||||
{
|
||||
void *fdt = initial_boot_params;
|
||||
const void *prop;
|
||||
int node, ret;
|
||||
bool dt_coh_set;
|
||||
|
||||
node = fdt_path_offset(fdt, path);
|
||||
if (node < 0)
|
||||
goto tweak_fail;
|
||||
|
||||
prop = fdt_getprop(fdt, node, "dma-coherent", &ret);
|
||||
if (!prop && ret != -FDT_ERR_NOTFOUND)
|
||||
goto tweak_fail;
|
||||
|
||||
dt_coh_set = ret != -FDT_ERR_NOTFOUND;
|
||||
ret = 0;
|
||||
|
||||
/* need to remove "dma-coherent" property */
|
||||
if (dt_coh_set && !coherent)
|
||||
ret = fdt_delprop(fdt, node, "dma-coherent");
|
||||
|
||||
/* need to set "dma-coherent" property */
|
||||
if (!dt_coh_set && coherent)
|
||||
ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0);
|
||||
|
||||
if (ret < 0)
|
||||
goto tweak_fail;
|
||||
|
||||
return 0;
|
||||
|
||||
tweak_fail:
|
||||
pr_err("failed to tweak %s to %scoherent\n", path, coherent ? "" : "non");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
enum hsdk_axi_masters {
|
||||
M_HS_CORE = 0,
|
||||
M_HS_RTT,
|
||||
|
|
@ -162,6 +202,39 @@ enum hsdk_axi_masters {
|
|||
#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
|
||||
#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
|
||||
|
||||
static void __init hsdk_init_memory_bridge_axi_dmac(void)
|
||||
{
|
||||
bool coherent = !!arc_hsdk_axi_dmac_coherent;
|
||||
u32 axi_m_slv1, axi_m_oft1;
|
||||
|
||||
/*
|
||||
* Don't tweak memory bridge configuration if we failed to tweak DTB
|
||||
* as we will end up in a inconsistent state.
|
||||
*/
|
||||
if (hsdk_tweak_node_coherency("/soc/dmac@80000", coherent))
|
||||
return;
|
||||
|
||||
if (coherent) {
|
||||
axi_m_slv1 = 0x77999999;
|
||||
axi_m_oft1 = 0x76DCBA98;
|
||||
} else {
|
||||
axi_m_slv1 = 0x77777777;
|
||||
axi_m_oft1 = 0x76543210;
|
||||
}
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
|
||||
writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
|
||||
writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
|
||||
writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
|
||||
writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
|
||||
}
|
||||
|
||||
static void __init hsdk_init_memory_bridge(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
@ -227,24 +300,14 @@ static void __init hsdk_init_memory_bridge(void)
|
|||
writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
|
||||
writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
|
||||
writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
|
||||
|
||||
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
|
||||
writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
|
||||
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
|
||||
writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
|
||||
|
||||
writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
|
||||
writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
|
||||
writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
|
||||
writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
|
||||
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
|
||||
|
||||
hsdk_init_memory_bridge_axi_dmac();
|
||||
|
||||
/*
|
||||
* PAE remapping for DMA clients does not work due to an RTL bug, so
|
||||
* CREG_PAE register must be programmed to all zeroes, otherwise it
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@
|
|||
uart0: serial@0 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x0 0x2000>;
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 26 0>, <&edma 27 0>;
|
||||
|
|
@ -934,7 +934,7 @@
|
|||
uart1: serial@0 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x0 0x2000>;
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 28 0>, <&edma 29 0>;
|
||||
|
|
@ -966,7 +966,7 @@
|
|||
uart2: serial@0 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x0 0x2000>;
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <74>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 30 0>, <&edma 31 0>;
|
||||
|
|
@ -1614,7 +1614,7 @@
|
|||
uart3: serial@0 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x0 0x2000>;
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1644,7 +1644,7 @@
|
|||
uart4: serial@0 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x0 0x2000>;
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1674,7 +1674,7 @@
|
|||
uart5: serial@0 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x0 0x2000>;
|
||||
reg = <0x0 0x1000>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1758,6 +1758,8 @@
|
|||
|
||||
target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0xcc020 0x4>;
|
||||
reg-names = "rev";
|
||||
ti,hwmods = "d_can0";
|
||||
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
|
||||
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
|
||||
|
|
@ -1780,6 +1782,8 @@
|
|||
|
||||
target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0xd0020 0x4>;
|
||||
reg-names = "rev";
|
||||
ti,hwmods = "d_can1";
|
||||
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
|
||||
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
|
||||
|
|
|
|||
|
|
@ -234,13 +234,33 @@
|
|||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
|
||||
mmc3: mmc@47810000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
target-module@47810000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <29>;
|
||||
reg = <0x47810000 0x1000>;
|
||||
status = "disabled";
|
||||
reg = <0x478102fc 0x4>,
|
||||
<0x47810110 0x4>,
|
||||
<0x47810114 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x47810000 0x1000>;
|
||||
|
||||
mmc3: mmc@0 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <29>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb: usb@47400000 {
|
||||
|
|
|
|||
|
|
@ -228,13 +228,33 @@
|
|||
interrupt-names = "edma3_tcerrint";
|
||||
};
|
||||
|
||||
mmc3: mmc@47810000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x47810000 0x1000>;
|
||||
target-module@47810000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
reg = <0x478102fc 0x4>,
|
||||
<0x47810110 0x4>,
|
||||
<0x47810114 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x47810000 0x1000>;
|
||||
|
||||
mmc3: mmc@0 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
sham: sham@53100000 {
|
||||
|
|
|
|||
|
|
@ -1574,6 +1574,8 @@
|
|||
|
||||
target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0xcc020 0x4>;
|
||||
reg-names = "rev";
|
||||
ti,hwmods = "d_can0";
|
||||
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
|
||||
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
|
||||
|
|
@ -1593,6 +1595,8 @@
|
|||
|
||||
target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0xd0020 0x4>;
|
||||
reg-names = "rev";
|
||||
ti,hwmods = "d_can1";
|
||||
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
|
||||
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
|
||||
|
|
|
|||
|
|
@ -175,14 +175,9 @@
|
|||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
||||
pinctrl-names = "default", "hs";
|
||||
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
|
||||
pinctrl-1 = <&mmc1_pins_hs>;
|
||||
pinctrl-2 = <&mmc1_pins_sdr12>;
|
||||
pinctrl-3 = <&mmc1_pins_sdr25>;
|
||||
pinctrl-4 = <&mmc1_pins_sdr50>;
|
||||
pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
|
||||
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
|
|
|
|||
|
|
@ -16,14 +16,9 @@
|
|||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
||||
pinctrl-names = "default", "hs";
|
||||
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
|
||||
pinctrl-1 = <&mmc1_pins_hs>;
|
||||
pinctrl-2 = <&mmc1_pins_sdr12>;
|
||||
pinctrl-3 = <&mmc1_pins_sdr25>;
|
||||
pinctrl-4 = <&mmc1_pins_sdr50>;
|
||||
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
|
||||
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
|
|
|
|||
|
|
@ -24,14 +24,9 @@
|
|||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
||||
pinctrl-names = "default", "hs";
|
||||
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
|
||||
pinctrl-1 = <&mmc1_pins_hs>;
|
||||
pinctrl-2 = <&mmc1_pins_default>;
|
||||
pinctrl-3 = <&mmc1_pins_hs>;
|
||||
pinctrl-4 = <&mmc1_pins_sdr50>;
|
||||
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_conf>;
|
||||
pinctrl-6 = <&mmc1_pins_ddr50 &mmc1_iodelay_sdr104_conf>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
|
|
|
|||
|
|
@ -379,7 +379,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
&gpio7_target {
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle-on-init;
|
||||
};
|
||||
|
|
@ -430,6 +430,7 @@
|
|||
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
|
|
|
|||
|
|
@ -16,14 +16,9 @@
|
|||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
||||
pinctrl-names = "default", "hs";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
pinctrl-1 = <&mmc1_pins_hs>;
|
||||
pinctrl-2 = <&mmc1_pins_sdr12>;
|
||||
pinctrl-3 = <&mmc1_pins_sdr25>;
|
||||
pinctrl-4 = <&mmc1_pins_sdr50>;
|
||||
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
|
||||
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
|
||||
vmmc-supply = <&vdd_3v3>;
|
||||
vqmmc-supply = <&ldo1_reg>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,14 +16,9 @@
|
|||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
|
||||
pinctrl-names = "default", "hs";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
pinctrl-1 = <&mmc1_pins_hs>;
|
||||
pinctrl-2 = <&mmc1_pins_sdr12>;
|
||||
pinctrl-3 = <&mmc1_pins_sdr25>;
|
||||
pinctrl-4 = <&mmc1_pins_sdr50>;
|
||||
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
|
||||
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
|
||||
vmmc-supply = <&vdd_3v3>;
|
||||
vqmmc-supply = <&ldo1_reg>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -498,7 +498,7 @@
|
|||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
&gpio7_target {
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle-on-init;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1261,7 +1261,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
target-module@51000 { /* 0x48051000, ap 45 2e.0 */
|
||||
gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
ti,hwmods = "gpio7";
|
||||
reg = <0x51000 0x4>,
|
||||
|
|
@ -3025,7 +3025,7 @@
|
|||
|
||||
target-module@80000 { /* 0x48480000, ap 31 16.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x80000 0x4>;
|
||||
reg = <0x80020 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
|
|
@ -4577,7 +4577,7 @@
|
|||
|
||||
target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0xc000 0x4>;
|
||||
reg = <0xc020 0x4>;
|
||||
reg-names = "rev";
|
||||
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
*
|
||||
* Datamanual Revisions:
|
||||
*
|
||||
* AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
|
||||
* AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019
|
||||
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
|
||||
*
|
||||
*/
|
||||
|
|
@ -229,45 +229,45 @@
|
|||
|
||||
mmc3_pins_default: mmc3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_hs: mmc3_pins_hs {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_sdr12: mmc3_pins_sdr12 {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_sdr25: mmc3_pins_sdr25 {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -246,13 +246,13 @@
|
|||
reg = <0>;
|
||||
};
|
||||
|
||||
n25q128a13_2: flash@1 {
|
||||
n25q128a13_2: flash@2 {
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <66000000>;
|
||||
spi-rx-bus-width = <2>;
|
||||
reg = <1>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ for_each_frame: tst frame, mask @ Check for address exceptions
|
|||
|
||||
1003: ldr r2, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
|
||||
ldr r3, .Ldsi+4 @ adjust saved 'pc' back one
|
||||
teq r3, r2, lsr #10 @ instruction
|
||||
teq r3, r2, lsr #11 @ instruction
|
||||
subne r0, sv_pc, #4 @ allow for mov
|
||||
subeq r0, sv_pc, #8 @ allow for mov + stmia
|
||||
|
||||
|
|
|
|||
|
|
@ -126,6 +126,8 @@ restart:
|
|||
orr r11, r11, r13 @ mask all requested interrupts
|
||||
str r11, [r12, #OMAP1510_GPIO_INT_MASK]
|
||||
|
||||
str r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack all requested interrupts
|
||||
|
||||
ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
|
||||
beq hksw @ no - try next source
|
||||
|
||||
|
|
@ -133,7 +135,6 @@ restart:
|
|||
@@@@@@@@@@@@@@@@@@@@@@
|
||||
@ Keyboard clock FIQ mode interrupt handler
|
||||
@ r10 now contains KEYBRD_CLK_MASK, use it
|
||||
str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt
|
||||
bic r11, r11, r10 @ unmask it
|
||||
str r11, [r12, #OMAP1510_GPIO_INT_MASK]
|
||||
|
||||
|
|
|
|||
|
|
@ -70,9 +70,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
|
|||
* interrupts default to since commit 80ac93c27441
|
||||
* requires interrupt already acked and unmasked.
|
||||
*/
|
||||
if (irq_chip->irq_ack)
|
||||
irq_chip->irq_ack(d);
|
||||
if (irq_chip->irq_unmask)
|
||||
if (!WARN_ON_ONCE(!irq_chip->irq_unmask))
|
||||
irq_chip->irq_unmask(d);
|
||||
}
|
||||
for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
|
||||
|
|
|
|||
|
|
@ -127,6 +127,9 @@ static int __init omap4_sram_init(void)
|
|||
struct device_node *np;
|
||||
struct gen_pool *sram_pool;
|
||||
|
||||
if (!soc_is_omap44xx() && !soc_is_omap54xx())
|
||||
return 0;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
|
||||
if (!np)
|
||||
pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
|
||||
|
|
|
|||
|
|
@ -379,7 +379,8 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = {
|
|||
static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
|
||||
.rev_offs = 0x0,
|
||||
.sysc_offs = 0x4,
|
||||
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
|
||||
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_RESET_STATUS,
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type2,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -175,6 +175,11 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max_low,
|
|||
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
|
||||
int pfn_valid(unsigned long pfn)
|
||||
{
|
||||
phys_addr_t addr = __pfn_to_phys(pfn);
|
||||
|
||||
if (__phys_to_pfn(addr) != pfn)
|
||||
return 0;
|
||||
|
||||
return memblock_is_map_memory(__pfn_to_phys(pfn));
|
||||
}
|
||||
EXPORT_SYMBOL(pfn_valid);
|
||||
|
|
@ -628,7 +633,8 @@ static void update_sections_early(struct section_perm perms[], int n)
|
|||
if (t->flags & PF_KTHREAD)
|
||||
continue;
|
||||
for_each_thread(t, s)
|
||||
set_section_perms(perms, n, true, s->mm);
|
||||
if (s->mm)
|
||||
set_section_perms(perms, n, true, s->mm);
|
||||
}
|
||||
set_section_perms(perms, n, true, current->active_mm);
|
||||
set_section_perms(perms, n, true, &init_mm);
|
||||
|
|
|
|||
|
|
@ -339,6 +339,12 @@
|
|||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
|
|
|
|||
|
|
@ -2386,6 +2386,7 @@
|
|||
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
||||
clock-names = "ddr";
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "peripheral";
|
||||
g-rx-fifo-size = <192>;
|
||||
g-np-tx-fifo-size = <128>;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
|
||||
gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
tf_io: gpio-regulator-tf_io {
|
||||
|
|
|
|||
|
|
@ -316,6 +316,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
|
|||
regs->uregs[0] = -EINTR;
|
||||
break;
|
||||
}
|
||||
/* Else, fall through */
|
||||
case -ERESTARTNOINTR:
|
||||
regs->uregs[0] = regs->orig_r0;
|
||||
regs->ipc -= 4;
|
||||
|
|
@ -360,6 +361,7 @@ static void do_signal(struct pt_regs *regs)
|
|||
switch (regs->uregs[0]) {
|
||||
case -ERESTART_RESTARTBLOCK:
|
||||
regs->uregs[15] = __NR_restart_syscall;
|
||||
/* Fall through */
|
||||
case -ERESTARTNOHAND:
|
||||
case -ERESTARTSYS:
|
||||
case -ERESTARTNOINTR:
|
||||
|
|
|
|||
|
|
@ -660,8 +660,10 @@ long kvmppc_h_put_tce_indirect(struct kvm_vcpu *vcpu,
|
|||
}
|
||||
tce = be64_to_cpu(tce);
|
||||
|
||||
if (kvmppc_tce_to_ua(vcpu->kvm, tce, &ua))
|
||||
return H_PARAMETER;
|
||||
if (kvmppc_tce_to_ua(vcpu->kvm, tce, &ua)) {
|
||||
ret = H_PARAMETER;
|
||||
goto unlock_exit;
|
||||
}
|
||||
|
||||
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
|
||||
ret = kvmppc_tce_iommu_map(vcpu->kvm, stt,
|
||||
|
|
|
|||
|
|
@ -556,8 +556,10 @@ long kvmppc_rm_h_put_tce_indirect(struct kvm_vcpu *vcpu,
|
|||
unsigned long tce = be64_to_cpu(((u64 *)tces)[i]);
|
||||
|
||||
ua = 0;
|
||||
if (kvmppc_rm_tce_to_ua(vcpu->kvm, tce, &ua, NULL))
|
||||
return H_PARAMETER;
|
||||
if (kvmppc_rm_tce_to_ua(vcpu->kvm, tce, &ua, NULL)) {
|
||||
ret = H_PARAMETER;
|
||||
goto unlock_exit;
|
||||
}
|
||||
|
||||
list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
|
||||
ret = kvmppc_rm_tce_iommu_map(vcpu->kvm, stt,
|
||||
|
|
|
|||
|
|
@ -30,10 +30,6 @@ enum fixed_addresses {
|
|||
__end_of_fixed_addresses
|
||||
};
|
||||
|
||||
#define FIXADDR_SIZE (__end_of_fixed_addresses * PAGE_SIZE)
|
||||
#define FIXADDR_TOP (VMALLOC_START)
|
||||
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
|
||||
|
||||
#define FIXMAP_PAGE_IO PAGE_KERNEL
|
||||
|
||||
#define __early_set_fixmap __set_fixmap
|
||||
|
|
|
|||
|
|
@ -420,14 +420,22 @@ static inline void pgtable_cache_init(void)
|
|||
#define VMALLOC_END (PAGE_OFFSET - 1)
|
||||
#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
|
||||
|
||||
#define FIXADDR_TOP VMALLOC_START
|
||||
#ifdef CONFIG_64BIT
|
||||
#define FIXADDR_SIZE PMD_SIZE
|
||||
#else
|
||||
#define FIXADDR_SIZE PGDIR_SIZE
|
||||
#endif
|
||||
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
|
||||
|
||||
/*
|
||||
* Task size is 0x4000000000 for RV64 or 0xb800000 for RV32.
|
||||
* Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
|
||||
* Note that PGDIR_SIZE must evenly divide TASK_SIZE.
|
||||
*/
|
||||
#ifdef CONFIG_64BIT
|
||||
#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2)
|
||||
#else
|
||||
#define TASK_SIZE VMALLOC_START
|
||||
#define TASK_SIZE FIXADDR_START
|
||||
#endif
|
||||
|
||||
#include <asm-generic/pgtable.h>
|
||||
|
|
|
|||
|
|
@ -863,7 +863,7 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i
|
|||
break;
|
||||
case BPF_ALU64 | BPF_NEG: /* dst = -dst */
|
||||
/* lcgr %dst,%dst */
|
||||
EMIT4(0xb9130000, dst_reg, dst_reg);
|
||||
EMIT4(0xb9030000, dst_reg, dst_reg);
|
||||
break;
|
||||
/*
|
||||
* BPF_FROM_BE/LE
|
||||
|
|
@ -1049,8 +1049,8 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i
|
|||
/* llgf %w1,map.max_entries(%b2) */
|
||||
EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
|
||||
offsetof(struct bpf_array, map.max_entries));
|
||||
/* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
|
||||
EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3,
|
||||
/* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
|
||||
EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
|
||||
REG_W1, 0, 0xa);
|
||||
|
||||
/*
|
||||
|
|
@ -1076,8 +1076,10 @@ static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i
|
|||
* goto out;
|
||||
*/
|
||||
|
||||
/* sllg %r1,%b3,3: %r1 = index * 8 */
|
||||
EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, BPF_REG_3, REG_0, 3);
|
||||
/* llgfr %r1,%b3: %r1 = (u32) index */
|
||||
EMIT4(0xb9160000, REG_1, BPF_REG_3);
|
||||
/* sllg %r1,%r1,3: %r1 *= 8 */
|
||||
EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
|
||||
/* lg %r1,prog(%b2,%r1) */
|
||||
EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
|
||||
REG_1, offsetof(struct bpf_array, ptrs));
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -DDISABLE_BRANCH_PROFILING \
|
|||
|
||||
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), -ffreestanding)
|
||||
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), -fno-stack-protector)
|
||||
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), -Wno-address-of-packed-member)
|
||||
REALMODE_CFLAGS += $(call __cc-option, $(CC), $(REALMODE_CFLAGS), $(cc_stack_align4))
|
||||
export REALMODE_CFLAGS
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ static unsigned long find_trampoline_placement(void)
|
|||
|
||||
/* Find the first usable memory region under bios_start. */
|
||||
for (i = boot_params->e820_entries - 1; i >= 0; i--) {
|
||||
unsigned long new;
|
||||
unsigned long new = bios_start;
|
||||
|
||||
entry = &boot_params->e820_table[i];
|
||||
|
||||
|
|
|
|||
|
|
@ -661,10 +661,17 @@ fail:
|
|||
|
||||
throttle = perf_event_overflow(event, &data, ®s);
|
||||
out:
|
||||
if (throttle)
|
||||
if (throttle) {
|
||||
perf_ibs_stop(event, 0);
|
||||
else
|
||||
perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
|
||||
} else {
|
||||
period >>= 4;
|
||||
|
||||
if ((ibs_caps & IBS_CAPS_RDWROPCNT) &&
|
||||
(*config & IBS_OP_CNT_CTL))
|
||||
period |= *config & IBS_OP_CUR_CNT_RAND;
|
||||
|
||||
perf_ibs_enable_event(perf_ibs, hwc, period);
|
||||
}
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
|
|
|
|||
|
|
@ -3580,6 +3580,11 @@ static u64 bdw_limit_period(struct perf_event *event, u64 left)
|
|||
return left;
|
||||
}
|
||||
|
||||
static u64 nhm_limit_period(struct perf_event *event, u64 left)
|
||||
{
|
||||
return max(left, 32ULL);
|
||||
}
|
||||
|
||||
PMU_FORMAT_ATTR(event, "config:0-7" );
|
||||
PMU_FORMAT_ATTR(umask, "config:8-15" );
|
||||
PMU_FORMAT_ATTR(edge, "config:18" );
|
||||
|
|
@ -4624,6 +4629,7 @@ __init int intel_pmu_init(void)
|
|||
x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
|
||||
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
||||
x86_pmu.extra_regs = intel_nehalem_extra_regs;
|
||||
x86_pmu.limit_period = nhm_limit_period;
|
||||
|
||||
mem_attr = nhm_mem_events_attrs;
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#define HAVE_FUNCTION_GRAPH_RET_ADDR_PTR
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void mcount(void);
|
||||
extern atomic_t modifying_ftrace_code;
|
||||
extern void __fentry__(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -252,16 +252,20 @@ struct pebs_lbr {
|
|||
#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
|
||||
#define IBSCTL_LVT_OFFSET_MASK 0x0F
|
||||
|
||||
/* ibs fetch bits/masks */
|
||||
/* IBS fetch bits/masks */
|
||||
#define IBS_FETCH_RAND_EN (1ULL<<57)
|
||||
#define IBS_FETCH_VAL (1ULL<<49)
|
||||
#define IBS_FETCH_ENABLE (1ULL<<48)
|
||||
#define IBS_FETCH_CNT 0xFFFF0000ULL
|
||||
#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
|
||||
|
||||
/* ibs op bits/masks */
|
||||
/* lower 4 bits of the current count are ignored: */
|
||||
#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
|
||||
/*
|
||||
* IBS op bits/masks
|
||||
* The lower 7 bits of the current count are random bits
|
||||
* preloaded by hardware and ignored in software
|
||||
*/
|
||||
#define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
|
||||
#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
|
||||
#define IBS_OP_CNT_CTL (1ULL<<19)
|
||||
#define IBS_OP_VAL (1ULL<<18)
|
||||
#define IBS_OP_ENABLE (1ULL<<17)
|
||||
|
|
|
|||
|
|
@ -1179,6 +1179,10 @@ void clear_local_APIC(void)
|
|||
apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
|
||||
v = apic_read(APIC_LVT1);
|
||||
apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
|
||||
if (!x2apic_enabled()) {
|
||||
v = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
|
||||
apic_write(APIC_LDR, v);
|
||||
}
|
||||
if (maxlvt >= 4) {
|
||||
v = apic_read(APIC_LVTPC);
|
||||
apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
|
||||
|
|
|
|||
|
|
@ -38,32 +38,12 @@ static int bigsmp_early_logical_apicid(int cpu)
|
|||
return early_per_cpu(x86_cpu_to_apicid, cpu);
|
||||
}
|
||||
|
||||
static inline unsigned long calculate_ldr(int cpu)
|
||||
{
|
||||
unsigned long val, id;
|
||||
|
||||
val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
|
||||
id = per_cpu(x86_bios_cpu_apicid, cpu);
|
||||
val |= SET_APIC_LOGICAL_ID(id);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up the logical destination ID.
|
||||
*
|
||||
* Intel recommends to set DFR, LDR and TPR before enabling
|
||||
* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
|
||||
* document number 292116). So here it goes...
|
||||
* bigsmp enables physical destination mode
|
||||
* and doesn't use LDR and DFR
|
||||
*/
|
||||
static void bigsmp_init_apic_ldr(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
apic_write(APIC_DFR, APIC_DFR_FLAT);
|
||||
val = calculate_ldr(cpu);
|
||||
apic_write(APIC_LDR, val);
|
||||
}
|
||||
|
||||
static void bigsmp_setup_apic_routing(void)
|
||||
|
|
|
|||
|
|
@ -2438,7 +2438,13 @@ unsigned int arch_dynirq_lower_bound(unsigned int from)
|
|||
* dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
|
||||
* gsi_top if ioapic_dynirq_base hasn't been initialized yet.
|
||||
*/
|
||||
return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
|
||||
if (!ioapic_initialized)
|
||||
return gsi_top;
|
||||
/*
|
||||
* For DT enabled machines ioapic_dynirq_base is irrelevant and not
|
||||
* updated. So simply return @from if ioapic_dynirq_base == 0.
|
||||
*/
|
||||
return ioapic_dynirq_base ? : from;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
|
|
|
|||
|
|
@ -508,9 +508,12 @@ struct uprobe_xol_ops {
|
|||
void (*abort)(struct arch_uprobe *, struct pt_regs *);
|
||||
};
|
||||
|
||||
static inline int sizeof_long(void)
|
||||
static inline int sizeof_long(struct pt_regs *regs)
|
||||
{
|
||||
return in_ia32_syscall() ? 4 : 8;
|
||||
/*
|
||||
* Check registers for mode as in_xxx_syscall() does not apply here.
|
||||
*/
|
||||
return user_64bit_mode(regs) ? 8 : 4;
|
||||
}
|
||||
|
||||
static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
||||
|
|
@ -521,9 +524,9 @@ static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|||
|
||||
static int emulate_push_stack(struct pt_regs *regs, unsigned long val)
|
||||
{
|
||||
unsigned long new_sp = regs->sp - sizeof_long();
|
||||
unsigned long new_sp = regs->sp - sizeof_long(regs);
|
||||
|
||||
if (copy_to_user((void __user *)new_sp, &val, sizeof_long()))
|
||||
if (copy_to_user((void __user *)new_sp, &val, sizeof_long(regs)))
|
||||
return -EFAULT;
|
||||
|
||||
regs->sp = new_sp;
|
||||
|
|
@ -556,7 +559,7 @@ static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs
|
|||
long correction = utask->vaddr - utask->xol_vaddr;
|
||||
regs->ip += correction;
|
||||
} else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
|
||||
regs->sp += sizeof_long(); /* Pop incorrect return address */
|
||||
regs->sp += sizeof_long(regs); /* Pop incorrect return address */
|
||||
if (emulate_push_stack(regs, utask->vaddr + auprobe->defparam.ilen))
|
||||
return -ERESTART;
|
||||
}
|
||||
|
|
@ -675,7 +678,7 @@ static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|||
* "call" insn was executed out-of-line. Just restore ->sp and restart.
|
||||
* We could also restore ->ip and try to call branch_emulate_op() again.
|
||||
*/
|
||||
regs->sp += sizeof_long();
|
||||
regs->sp += sizeof_long(regs);
|
||||
return -ERESTART;
|
||||
}
|
||||
|
||||
|
|
@ -1056,7 +1059,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
|
|||
unsigned long
|
||||
arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
|
||||
{
|
||||
int rasize = sizeof_long(), nleft;
|
||||
int rasize = sizeof_long(regs), nleft;
|
||||
unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
|
||||
|
||||
if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
|
||||
|
|
|
|||
|
|
@ -1781,7 +1781,7 @@ int kvm_vm_ioctl_hv_eventfd(struct kvm *kvm, struct kvm_hyperv_eventfd *args)
|
|||
int kvm_vcpu_ioctl_get_hv_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid2 *cpuid,
|
||||
struct kvm_cpuid_entry2 __user *entries)
|
||||
{
|
||||
uint16_t evmcs_ver = kvm_x86_ops->nested_get_evmcs_version(vcpu);
|
||||
uint16_t evmcs_ver = 0;
|
||||
struct kvm_cpuid_entry2 cpuid_entries[] = {
|
||||
{ .function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS },
|
||||
{ .function = HYPERV_CPUID_INTERFACE },
|
||||
|
|
@ -1793,6 +1793,9 @@ int kvm_vcpu_ioctl_get_hv_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid2 *cpuid,
|
|||
};
|
||||
int i, nent = ARRAY_SIZE(cpuid_entries);
|
||||
|
||||
if (kvm_x86_ops->nested_get_evmcs_version)
|
||||
evmcs_ver = kvm_x86_ops->nested_get_evmcs_version(vcpu);
|
||||
|
||||
/* Skip NESTED_FEATURES if eVMCS is not supported */
|
||||
if (!evmcs_ver)
|
||||
--nent;
|
||||
|
|
|
|||
|
|
@ -7128,12 +7128,6 @@ failed:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
/* Not supported */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
|
||||
uint16_t *vmcs_version)
|
||||
{
|
||||
|
|
@ -7332,7 +7326,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
|
|||
.mem_enc_unreg_region = svm_unregister_enc_region,
|
||||
|
||||
.nested_enable_evmcs = nested_enable_evmcs,
|
||||
.nested_get_evmcs_version = nested_get_evmcs_version,
|
||||
.nested_get_evmcs_version = NULL,
|
||||
|
||||
.need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7797,6 +7797,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
|
|||
.set_nested_state = NULL,
|
||||
.get_vmcs12_pages = NULL,
|
||||
.nested_enable_evmcs = NULL,
|
||||
.nested_get_evmcs_version = NULL,
|
||||
.need_emulation_on_page_fault = vmx_need_emulation_on_page_fault,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -6594,12 +6594,13 @@ restart:
|
|||
unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
|
||||
toggle_interruptibility(vcpu, ctxt->interruptibility);
|
||||
vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
|
||||
kvm_rip_write(vcpu, ctxt->eip);
|
||||
if (r == EMULATE_DONE && ctxt->tf)
|
||||
kvm_vcpu_do_singlestep(vcpu, &r);
|
||||
if (!ctxt->have_exception ||
|
||||
exception_type(ctxt->exception.vector) == EXCPT_TRAP)
|
||||
exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
|
||||
kvm_rip_write(vcpu, ctxt->eip);
|
||||
if (r == EMULATE_DONE && ctxt->tf)
|
||||
kvm_vcpu_do_singlestep(vcpu, &r);
|
||||
__kvm_set_rflags(vcpu, ctxt->eflags);
|
||||
}
|
||||
|
||||
/*
|
||||
* For STI, interrupts are shadowed; so KVM_REQ_EVENT will
|
||||
|
|
|
|||
|
|
@ -516,7 +516,7 @@ static inline void check_conflict(int warnlvl, pgprot_t prot, pgprotval_t val,
|
|||
*/
|
||||
static inline pgprot_t static_protections(pgprot_t prot, unsigned long start,
|
||||
unsigned long pfn, unsigned long npg,
|
||||
int warnlvl)
|
||||
unsigned long lpsize, int warnlvl)
|
||||
{
|
||||
pgprotval_t forbidden, res;
|
||||
unsigned long end;
|
||||
|
|
@ -535,9 +535,17 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long start,
|
|||
check_conflict(warnlvl, prot, res, start, end, pfn, "Text NX");
|
||||
forbidden = res;
|
||||
|
||||
res = protect_kernel_text_ro(start, end);
|
||||
check_conflict(warnlvl, prot, res, start, end, pfn, "Text RO");
|
||||
forbidden |= res;
|
||||
/*
|
||||
* Special case to preserve a large page. If the change spawns the
|
||||
* full large page mapping then there is no point to split it
|
||||
* up. Happens with ftrace and is going to be removed once ftrace
|
||||
* switched to text_poke().
|
||||
*/
|
||||
if (lpsize != (npg * PAGE_SIZE) || (start & (lpsize - 1))) {
|
||||
res = protect_kernel_text_ro(start, end);
|
||||
check_conflict(warnlvl, prot, res, start, end, pfn, "Text RO");
|
||||
forbidden |= res;
|
||||
}
|
||||
|
||||
/* Check the PFN directly */
|
||||
res = protect_pci_bios(pfn, pfn + npg - 1);
|
||||
|
|
@ -819,7 +827,7 @@ static int __should_split_large_page(pte_t *kpte, unsigned long address,
|
|||
* extra conditional required here.
|
||||
*/
|
||||
chk_prot = static_protections(old_prot, lpaddr, old_pfn, numpages,
|
||||
CPA_CONFLICT);
|
||||
psize, CPA_CONFLICT);
|
||||
|
||||
if (WARN_ON_ONCE(pgprot_val(chk_prot) != pgprot_val(old_prot))) {
|
||||
/*
|
||||
|
|
@ -855,7 +863,7 @@ static int __should_split_large_page(pte_t *kpte, unsigned long address,
|
|||
* protection requirement in the large page.
|
||||
*/
|
||||
new_prot = static_protections(req_prot, lpaddr, old_pfn, numpages,
|
||||
CPA_DETECT);
|
||||
psize, CPA_DETECT);
|
||||
|
||||
/*
|
||||
* If there is a conflict, split the large page.
|
||||
|
|
@ -906,7 +914,8 @@ static void split_set_pte(struct cpa_data *cpa, pte_t *pte, unsigned long pfn,
|
|||
if (!cpa->force_static_prot)
|
||||
goto set;
|
||||
|
||||
prot = static_protections(ref_prot, address, pfn, npg, CPA_PROTECT);
|
||||
/* Hand in lpsize = 0 to enforce the protection mechanism */
|
||||
prot = static_protections(ref_prot, address, pfn, npg, 0, CPA_PROTECT);
|
||||
|
||||
if (pgprot_val(prot) == pgprot_val(ref_prot))
|
||||
goto set;
|
||||
|
|
@ -1503,7 +1512,8 @@ repeat:
|
|||
pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
|
||||
|
||||
cpa_inc_4k_install();
|
||||
new_prot = static_protections(new_prot, address, pfn, 1,
|
||||
/* Hand in lpsize = 0 to enforce the protection mechanism */
|
||||
new_prot = static_protections(new_prot, address, pfn, 1, 0,
|
||||
CPA_PROTECT);
|
||||
|
||||
new_prot = pgprot_clear_protnone_bits(new_prot);
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ config ATM_NICSTAR_USE_SUNI
|
|||
make the card work).
|
||||
|
||||
config ATM_NICSTAR_USE_IDT77105
|
||||
bool "Use IDT77015 PHY driver (25Mbps)"
|
||||
bool "Use IDT77105 PHY driver (25Mbps)"
|
||||
depends on ATM_NICSTAR
|
||||
help
|
||||
Support for the PHYsical layer chip in ForeRunner LE25 cards. In
|
||||
|
|
|
|||
|
|
@ -3038,6 +3038,17 @@ again:
|
|||
}
|
||||
return true;
|
||||
case RBD_OBJ_READ_PARENT:
|
||||
/*
|
||||
* The parent image is read only up to the overlap -- zero-fill
|
||||
* from the overlap to the end of the request.
|
||||
*/
|
||||
if (!*result) {
|
||||
u32 obj_overlap = rbd_obj_img_extents_bytes(obj_req);
|
||||
|
||||
if (obj_overlap < obj_req->ex.oe_len)
|
||||
rbd_obj_zero_range(obj_req, obj_overlap,
|
||||
obj_req->ex.oe_len - obj_overlap);
|
||||
}
|
||||
return true;
|
||||
default:
|
||||
BUG();
|
||||
|
|
|
|||
|
|
@ -456,6 +456,17 @@ struct hisi_lpc_acpi_cell {
|
|||
size_t pdata_size;
|
||||
};
|
||||
|
||||
static void hisi_lpc_acpi_remove(struct device *hostdev)
|
||||
{
|
||||
struct acpi_device *adev = ACPI_COMPANION(hostdev);
|
||||
struct acpi_device *child;
|
||||
|
||||
device_for_each_child(hostdev, NULL, hisi_lpc_acpi_remove_subdev);
|
||||
|
||||
list_for_each_entry(child, &adev->children, node)
|
||||
acpi_device_clear_enumerated(child);
|
||||
}
|
||||
|
||||
/*
|
||||
* hisi_lpc_acpi_probe - probe children for ACPI FW
|
||||
* @hostdev: LPC host device pointer
|
||||
|
|
@ -555,8 +566,7 @@ static int hisi_lpc_acpi_probe(struct device *hostdev)
|
|||
return 0;
|
||||
|
||||
fail:
|
||||
device_for_each_child(hostdev, NULL,
|
||||
hisi_lpc_acpi_remove_subdev);
|
||||
hisi_lpc_acpi_remove(hostdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -569,6 +579,10 @@ static int hisi_lpc_acpi_probe(struct device *dev)
|
|||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void hisi_lpc_acpi_remove(struct device *hostdev)
|
||||
{
|
||||
}
|
||||
#endif // CONFIG_ACPI
|
||||
|
||||
/*
|
||||
|
|
@ -606,24 +620,27 @@ static int hisi_lpc_probe(struct platform_device *pdev)
|
|||
range->fwnode = dev->fwnode;
|
||||
range->flags = LOGIC_PIO_INDIRECT;
|
||||
range->size = PIO_INDIRECT_SIZE;
|
||||
range->hostdata = lpcdev;
|
||||
range->ops = &hisi_lpc_ops;
|
||||
lpcdev->io_host = range;
|
||||
|
||||
ret = logic_pio_register_range(range);
|
||||
if (ret) {
|
||||
dev_err(dev, "register IO range failed (%d)!\n", ret);
|
||||
return ret;
|
||||
}
|
||||
lpcdev->io_host = range;
|
||||
|
||||
/* register the LPC host PIO resources */
|
||||
if (acpi_device)
|
||||
ret = hisi_lpc_acpi_probe(dev);
|
||||
else
|
||||
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
logic_pio_unregister_range(range);
|
||||
return ret;
|
||||
}
|
||||
|
||||
lpcdev->io_host->hostdata = lpcdev;
|
||||
lpcdev->io_host->ops = &hisi_lpc_ops;
|
||||
dev_set_drvdata(dev, lpcdev);
|
||||
|
||||
io_end = lpcdev->io_host->io_start + lpcdev->io_host->size;
|
||||
dev_info(dev, "registered range [%pa - %pa]\n",
|
||||
|
|
@ -632,6 +649,23 @@ static int hisi_lpc_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int hisi_lpc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct acpi_device *acpi_device = ACPI_COMPANION(dev);
|
||||
struct hisi_lpc_dev *lpcdev = dev_get_drvdata(dev);
|
||||
struct logic_pio_hwaddr *range = lpcdev->io_host;
|
||||
|
||||
if (acpi_device)
|
||||
hisi_lpc_acpi_remove(dev);
|
||||
else
|
||||
of_platform_depopulate(dev);
|
||||
|
||||
logic_pio_unregister_range(range);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id hisi_lpc_of_match[] = {
|
||||
{ .compatible = "hisilicon,hip06-lpc", },
|
||||
{ .compatible = "hisilicon,hip07-lpc", },
|
||||
|
|
@ -645,5 +679,6 @@ static struct platform_driver hisi_lpc_driver = {
|
|||
.acpi_match_table = ACPI_PTR(hisi_lpc_acpi_match),
|
||||
},
|
||||
.probe = hisi_lpc_probe,
|
||||
.remove = hisi_lpc_remove,
|
||||
};
|
||||
builtin_platform_driver(hisi_lpc_driver);
|
||||
|
|
|
|||
|
|
@ -949,7 +949,7 @@ static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
|
|||
*best_mode = SYSC_IDLE_SMART_WKUP;
|
||||
else if (idlemodes & BIT(SYSC_IDLE_SMART))
|
||||
*best_mode = SYSC_IDLE_SMART;
|
||||
else if (idlemodes & SYSC_IDLE_FORCE)
|
||||
else if (idlemodes & BIT(SYSC_IDLE_FORCE))
|
||||
*best_mode = SYSC_IDLE_FORCE;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
|
@ -1267,7 +1267,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
|
|||
SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
|
||||
SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
|
||||
0xffff00f0, 0),
|
||||
SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
|
||||
SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
|
||||
SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
|
||||
SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
|
||||
SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
|
||||
SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
|
||||
|
|
@ -1692,10 +1693,7 @@ static int sysc_init_sysc_mask(struct sysc *ddata)
|
|||
if (error)
|
||||
return 0;
|
||||
|
||||
if (val)
|
||||
ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
|
||||
else
|
||||
ddata->cfg.sysc_val = ddata->cap->sysc_mask;
|
||||
ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2385,27 +2383,27 @@ static int sysc_probe(struct platform_device *pdev)
|
|||
|
||||
error = sysc_init_dts_quirks(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
return error;
|
||||
|
||||
error = sysc_map_and_check_registers(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
return error;
|
||||
|
||||
error = sysc_init_sysc_mask(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
return error;
|
||||
|
||||
error = sysc_init_idlemodes(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
return error;
|
||||
|
||||
error = sysc_init_syss_mask(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
return error;
|
||||
|
||||
error = sysc_init_pdata(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
return error;
|
||||
|
||||
sysc_init_early_quirks(ddata);
|
||||
|
||||
|
|
@ -2415,7 +2413,7 @@ static int sysc_probe(struct platform_device *pdev)
|
|||
|
||||
error = sysc_init_resets(ddata);
|
||||
if (error)
|
||||
return error;
|
||||
goto unprepare;
|
||||
|
||||
error = sysc_init_module(ddata);
|
||||
if (error)
|
||||
|
|
|
|||
|
|
@ -540,6 +540,10 @@ int ccp_dev_suspend(struct sp_device *sp, pm_message_t state)
|
|||
unsigned long flags;
|
||||
unsigned int i;
|
||||
|
||||
/* If there's no device there's nothing to do */
|
||||
if (!ccp)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&ccp->cmd_lock, flags);
|
||||
|
||||
ccp->suspending = 1;
|
||||
|
|
@ -564,6 +568,10 @@ int ccp_dev_resume(struct sp_device *sp)
|
|||
unsigned long flags;
|
||||
unsigned int i;
|
||||
|
||||
/* If there's no device there's nothing to do */
|
||||
if (!ccp)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&ccp->cmd_lock, flags);
|
||||
|
||||
ccp->suspending = 0;
|
||||
|
|
|
|||
|
|
@ -574,6 +574,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
|
|||
{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
||||
{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
||||
{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
||||
{ 0x1002, 0x699f, 0x1028, 0x0814, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
||||
{ 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
||||
{ 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
||||
{ 0, 0, 0, 0, 0 },
|
||||
|
|
|
|||
|
|
@ -534,21 +534,24 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
|
|||
struct drm_sched_entity *entity)
|
||||
{
|
||||
struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity);
|
||||
unsigned idx = centity->sequence & (amdgpu_sched_jobs - 1);
|
||||
struct dma_fence *other = centity->fences[idx];
|
||||
struct dma_fence *other;
|
||||
unsigned idx;
|
||||
long r;
|
||||
|
||||
if (other) {
|
||||
signed long r;
|
||||
r = dma_fence_wait(other, true);
|
||||
if (r < 0) {
|
||||
if (r != -ERESTARTSYS)
|
||||
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
|
||||
spin_lock(&ctx->ring_lock);
|
||||
idx = centity->sequence & (amdgpu_sched_jobs - 1);
|
||||
other = dma_fence_get(centity->fences[idx]);
|
||||
spin_unlock(&ctx->ring_lock);
|
||||
|
||||
return r;
|
||||
}
|
||||
}
|
||||
if (!other)
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
r = dma_fence_wait(other, true);
|
||||
if (r < 0 && r != -ERESTARTSYS)
|
||||
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
|
||||
|
||||
dma_fence_put(other);
|
||||
return r;
|
||||
}
|
||||
|
||||
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
|
||||
|
|
|
|||
|
|
@ -596,14 +596,14 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
|
|||
case CHIP_VEGA20:
|
||||
break;
|
||||
case CHIP_RAVEN:
|
||||
if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
|
||||
break;
|
||||
if ((adev->gfx.rlc_fw_version != 106 &&
|
||||
adev->gfx.rlc_fw_version < 531) ||
|
||||
(adev->gfx.rlc_fw_version == 53815) ||
|
||||
(adev->gfx.rlc_feature_version < 1) ||
|
||||
!adev->gfx.rlc.is_rlc_v2_1)
|
||||
if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
|
||||
&&((adev->gfx.rlc_fw_version != 106 &&
|
||||
adev->gfx.rlc_fw_version < 531) ||
|
||||
(adev->gfx.rlc_fw_version == 53815) ||
|
||||
(adev->gfx.rlc_feature_version < 1) ||
|
||||
!adev->gfx.rlc.is_rlc_v2_1))
|
||||
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
|
||||
|
||||
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
|
||||
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
|
||||
AMD_PG_SUPPORT_CP |
|
||||
|
|
|
|||
|
|
@ -2101,7 +2101,11 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
*query = metrics_table.CurrSocketPower << 8;
|
||||
/* For the 40.46 release, they changed the value name */
|
||||
if (hwmgr->smu_version == 0x282e00)
|
||||
*query = metrics_table.AverageSocketPower << 8;
|
||||
else
|
||||
*query = metrics_table.CurrSocketPower << 8;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -2349,12 +2353,16 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
|
|||
data->dpm_table.soc_table.dpm_state.soft_max_level =
|
||||
data->dpm_table.soc_table.dpm_levels[soft_level].value;
|
||||
|
||||
ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
|
||||
ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
|
||||
FEATURE_DPM_UCLK_MASK |
|
||||
FEATURE_DPM_SOCCLK_MASK);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"Failed to upload boot level to highest!",
|
||||
return ret);
|
||||
|
||||
ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
|
||||
ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
|
||||
FEATURE_DPM_UCLK_MASK |
|
||||
FEATURE_DPM_SOCCLK_MASK);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"Failed to upload dpm max level to highest!",
|
||||
return ret);
|
||||
|
|
@ -2387,12 +2395,16 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
|
|||
data->dpm_table.soc_table.dpm_state.soft_max_level =
|
||||
data->dpm_table.soc_table.dpm_levels[soft_level].value;
|
||||
|
||||
ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
|
||||
ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
|
||||
FEATURE_DPM_UCLK_MASK |
|
||||
FEATURE_DPM_SOCCLK_MASK);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"Failed to upload boot level to highest!",
|
||||
return ret);
|
||||
|
||||
ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
|
||||
ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
|
||||
FEATURE_DPM_UCLK_MASK |
|
||||
FEATURE_DPM_SOCCLK_MASK);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"Failed to upload dpm max level to highest!",
|
||||
return ret);
|
||||
|
|
@ -2403,14 +2415,54 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
|
|||
|
||||
static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct vega20_hwmgr *data =
|
||||
(struct vega20_hwmgr *)(hwmgr->backend);
|
||||
uint32_t soft_min_level, soft_max_level;
|
||||
int ret = 0;
|
||||
|
||||
ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
|
||||
/* gfxclk soft min/max settings */
|
||||
soft_min_level =
|
||||
vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
|
||||
soft_max_level =
|
||||
vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
|
||||
|
||||
data->dpm_table.gfx_table.dpm_state.soft_min_level =
|
||||
data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
|
||||
data->dpm_table.gfx_table.dpm_state.soft_max_level =
|
||||
data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
|
||||
|
||||
/* uclk soft min/max settings */
|
||||
soft_min_level =
|
||||
vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
|
||||
soft_max_level =
|
||||
vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
|
||||
|
||||
data->dpm_table.mem_table.dpm_state.soft_min_level =
|
||||
data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
|
||||
data->dpm_table.mem_table.dpm_state.soft_max_level =
|
||||
data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
|
||||
|
||||
/* socclk soft min/max settings */
|
||||
soft_min_level =
|
||||
vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
|
||||
soft_max_level =
|
||||
vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
|
||||
|
||||
data->dpm_table.soc_table.dpm_state.soft_min_level =
|
||||
data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
|
||||
data->dpm_table.soc_table.dpm_state.soft_max_level =
|
||||
data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
|
||||
|
||||
ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
|
||||
FEATURE_DPM_UCLK_MASK |
|
||||
FEATURE_DPM_SOCCLK_MASK);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"Failed to upload DPM Bootup Levels!",
|
||||
return ret);
|
||||
|
||||
ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
|
||||
ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
|
||||
FEATURE_DPM_UCLK_MASK |
|
||||
FEATURE_DPM_SOCCLK_MASK);
|
||||
PP_ASSERT_WITH_CODE(!ret,
|
||||
"Failed to upload DPM Max Levels!",
|
||||
return ret);
|
||||
|
|
|
|||
|
|
@ -3050,6 +3050,7 @@ static int vega20_get_fan_speed_percent(struct smu_context *smu,
|
|||
|
||||
static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
|
||||
{
|
||||
uint32_t smu_version;
|
||||
int ret = 0;
|
||||
SmuMetrics_t metrics;
|
||||
|
||||
|
|
@ -3060,7 +3061,15 @@ static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
*value = metrics.CurrSocketPower << 8;
|
||||
ret = smu_get_smc_version(smu, NULL, &smu_version);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* For the 40.46 release, they changed the value name */
|
||||
if (smu_version == 0x282e00)
|
||||
*value = metrics.AverageSocketPower << 8;
|
||||
else
|
||||
*value = metrics.CurrSocketPower << 8;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)
|
|||
pipe->of_output_port =
|
||||
of_graph_get_port_by_id(np, KOMEDA_OF_PORT_OUTPUT);
|
||||
|
||||
pipe->of_node = np;
|
||||
pipe->of_node = of_node_get(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,8 +14,8 @@
|
|||
#include <drm/drm_gem_cma_helper.h>
|
||||
#include <drm/drm_gem_framebuffer_helper.h>
|
||||
#include <drm/drm_irq.h>
|
||||
#include <drm/drm_vblank.h>
|
||||
#include <drm/drm_probe_helper.h>
|
||||
#include <drm/drm_vblank.h>
|
||||
|
||||
#include "komeda_dev.h"
|
||||
#include "komeda_framebuffer.h"
|
||||
|
|
@ -147,7 +147,6 @@ static int komeda_crtc_normalize_zpos(struct drm_crtc *crtc,
|
|||
struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_st);
|
||||
struct komeda_plane_state *kplane_st;
|
||||
struct drm_plane_state *plane_st;
|
||||
struct drm_framebuffer *fb;
|
||||
struct drm_plane *plane;
|
||||
struct list_head zorder_list;
|
||||
int order = 0, err;
|
||||
|
|
@ -173,7 +172,6 @@ static int komeda_crtc_normalize_zpos(struct drm_crtc *crtc,
|
|||
|
||||
list_for_each_entry(kplane_st, &zorder_list, zlist_node) {
|
||||
plane_st = &kplane_st->base;
|
||||
fb = plane_st->fb;
|
||||
plane = plane_st->plane;
|
||||
|
||||
plane_st->normalized_zpos = order++;
|
||||
|
|
@ -206,7 +204,7 @@ static int komeda_kms_check(struct drm_device *dev,
|
|||
struct drm_atomic_state *state)
|
||||
{
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_crtc_state *old_crtc_st, *new_crtc_st;
|
||||
struct drm_crtc_state *new_crtc_st;
|
||||
int i, err;
|
||||
|
||||
err = drm_atomic_helper_check_modeset(dev, state);
|
||||
|
|
@ -217,7 +215,7 @@ static int komeda_kms_check(struct drm_device *dev,
|
|||
* so need to add all affected_planes (even unchanged) to
|
||||
* drm_atomic_state.
|
||||
*/
|
||||
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_st, new_crtc_st, i) {
|
||||
for_each_new_crtc_in_state(state, crtc, new_crtc_st, i) {
|
||||
err = drm_atomic_add_affected_planes(state, crtc);
|
||||
if (err)
|
||||
return err;
|
||||
|
|
@ -308,11 +306,11 @@ struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev)
|
|||
komeda_kms_irq_handler, IRQF_SHARED,
|
||||
drm->driver->name, drm);
|
||||
if (err)
|
||||
goto cleanup_mode_config;
|
||||
goto free_component_binding;
|
||||
|
||||
err = mdev->funcs->enable_irq(mdev);
|
||||
if (err)
|
||||
goto cleanup_mode_config;
|
||||
goto free_component_binding;
|
||||
|
||||
drm->irq_enabled = true;
|
||||
|
||||
|
|
@ -320,15 +318,21 @@ struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev)
|
|||
|
||||
err = drm_dev_register(drm, 0);
|
||||
if (err)
|
||||
goto cleanup_mode_config;
|
||||
goto free_interrupts;
|
||||
|
||||
return kms;
|
||||
|
||||
cleanup_mode_config:
|
||||
free_interrupts:
|
||||
drm_kms_helper_poll_fini(drm);
|
||||
drm->irq_enabled = false;
|
||||
mdev->funcs->disable_irq(mdev);
|
||||
free_component_binding:
|
||||
component_unbind_all(mdev->dev, drm);
|
||||
cleanup_mode_config:
|
||||
drm_mode_config_cleanup(drm);
|
||||
komeda_kms_cleanup_private_objs(kms);
|
||||
drm->dev_private = NULL;
|
||||
drm_dev_put(drm);
|
||||
free_kms:
|
||||
kfree(kms);
|
||||
return ERR_PTR(err);
|
||||
|
|
@ -339,13 +343,14 @@ void komeda_kms_detach(struct komeda_kms_dev *kms)
|
|||
struct drm_device *drm = &kms->base;
|
||||
struct komeda_dev *mdev = drm->dev_private;
|
||||
|
||||
drm->irq_enabled = false;
|
||||
mdev->funcs->disable_irq(mdev);
|
||||
drm_dev_unregister(drm);
|
||||
drm_kms_helper_poll_fini(drm);
|
||||
drm_atomic_helper_shutdown(drm);
|
||||
drm->irq_enabled = false;
|
||||
mdev->funcs->disable_irq(mdev);
|
||||
component_unbind_all(mdev->dev, drm);
|
||||
komeda_kms_cleanup_private_objs(kms);
|
||||
drm_mode_config_cleanup(drm);
|
||||
komeda_kms_cleanup_private_objs(kms);
|
||||
drm->dev_private = NULL;
|
||||
drm_dev_put(drm);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -480,6 +480,7 @@ void komeda_pipeline_dump_register(struct komeda_pipeline *pipe,
|
|||
struct seq_file *sf);
|
||||
|
||||
/* component APIs */
|
||||
extern __printf(10, 11)
|
||||
struct komeda_component *
|
||||
komeda_component_add(struct komeda_pipeline *pipe,
|
||||
size_t comp_sz, u32 id, u32 hw_id,
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ static int komeda_wb_connector_add(struct komeda_kms_dev *kms,
|
|||
if (!kcrtc->master->wb_layer)
|
||||
return 0;
|
||||
|
||||
kwb_conn = kzalloc(sizeof(*wb_conn), GFP_KERNEL);
|
||||
kwb_conn = kzalloc(sizeof(*kwb_conn), GFP_KERNEL);
|
||||
if (!kwb_conn)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
|
|||
|
|
@ -539,7 +539,15 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
|
|||
|
||||
intel_attach_force_audio_property(connector);
|
||||
intel_attach_broadcast_rgb_property(connector);
|
||||
drm_connector_attach_max_bpc_property(connector, 6, 12);
|
||||
|
||||
/*
|
||||
* Reuse the prop from the SST connector because we're
|
||||
* not allowed to create new props after device registration.
|
||||
*/
|
||||
connector->max_bpc_property =
|
||||
intel_dp->attached_connector->base.max_bpc_property;
|
||||
if (connector->max_bpc_property)
|
||||
drm_connector_attach_max_bpc_property(connector, 6, 12);
|
||||
|
||||
return connector;
|
||||
|
||||
|
|
|
|||
|
|
@ -541,7 +541,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
|
|||
pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
|
||||
DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
|
||||
DRM_INFO("PPS2 = 0x%08x\n", pps_val);
|
||||
if (encoder->type == INTEL_OUTPUT_EDP) {
|
||||
if (cpu_transcoder == TRANSCODER_EDP) {
|
||||
I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
|
||||
/*
|
||||
* If 2 VDSC instances are needed, configure PPS for second
|
||||
|
|
|
|||
|
|
@ -1598,6 +1598,12 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
|
|||
|
||||
pci_set_master(pdev);
|
||||
|
||||
/*
|
||||
* We don't have a max segment size, so set it to the max so sg's
|
||||
* debugging layer doesn't complain
|
||||
*/
|
||||
dma_set_max_seg_size(&pdev->dev, UINT_MAX);
|
||||
|
||||
/* overlay on gen2 is broken and can't address above 1G */
|
||||
if (IS_GEN(dev_priv, 2)) {
|
||||
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
|
||||
|
|
|
|||
|
|
@ -101,6 +101,9 @@ static struct _balloon_info_ bl_info;
|
|||
static void vgt_deballoon_space(struct i915_ggtt *ggtt,
|
||||
struct drm_mm_node *node)
|
||||
{
|
||||
if (!drm_mm_node_allocated(node))
|
||||
return;
|
||||
|
||||
DRM_DEBUG_DRIVER("deballoon space: range [0x%llx - 0x%llx] %llu KiB.\n",
|
||||
node->start,
|
||||
node->start + node->size,
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* Author: Archit Taneja <archit@ti.com>
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -20,7 +21,8 @@ int omapdss_device_init_output(struct omap_dss_device *out)
|
|||
{
|
||||
struct device_node *remote_node;
|
||||
|
||||
remote_node = of_graph_get_remote_node(out->dev->of_node, 0, 0);
|
||||
remote_node = of_graph_get_remote_node(out->dev->of_node,
|
||||
ffs(out->of_ports) - 1, 0);
|
||||
if (!remote_node) {
|
||||
dev_dbg(out->dev, "failed to find video sink\n");
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -59,6 +59,11 @@ module_param_named(num_heads, qxl_num_crtc, int, 0400);
|
|||
static struct drm_driver qxl_driver;
|
||||
static struct pci_driver qxl_pci_driver;
|
||||
|
||||
static bool is_vga(struct pci_dev *pdev)
|
||||
{
|
||||
return pdev->class == PCI_CLASS_DISPLAY_VGA << 8;
|
||||
}
|
||||
|
||||
static int
|
||||
qxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
|
|
@ -83,9 +88,17 @@ qxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (ret)
|
||||
goto disable_pci;
|
||||
|
||||
if (is_vga(pdev)) {
|
||||
ret = vga_get_interruptible(pdev, VGA_RSRC_LEGACY_IO);
|
||||
if (ret) {
|
||||
DRM_ERROR("can't get legacy vga ioports\n");
|
||||
goto disable_pci;
|
||||
}
|
||||
}
|
||||
|
||||
ret = qxl_device_init(qdev, &qxl_driver, pdev);
|
||||
if (ret)
|
||||
goto disable_pci;
|
||||
goto put_vga;
|
||||
|
||||
ret = qxl_modeset_init(qdev);
|
||||
if (ret)
|
||||
|
|
@ -105,6 +118,9 @@ modeset_cleanup:
|
|||
qxl_modeset_fini(qdev);
|
||||
unload:
|
||||
qxl_device_fini(qdev);
|
||||
put_vga:
|
||||
if (is_vga(pdev))
|
||||
vga_put(pdev, VGA_RSRC_LEGACY_IO);
|
||||
disable_pci:
|
||||
pci_disable_device(pdev);
|
||||
free_dev:
|
||||
|
|
@ -122,6 +138,8 @@ qxl_pci_remove(struct pci_dev *pdev)
|
|||
|
||||
qxl_modeset_fini(qdev);
|
||||
qxl_device_fini(qdev);
|
||||
if (is_vga(pdev))
|
||||
vga_put(pdev, VGA_RSRC_LEGACY_IO);
|
||||
|
||||
dev->dev_private = NULL;
|
||||
kfree(qdev);
|
||||
|
|
|
|||
|
|
@ -204,6 +204,7 @@ int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
|
|||
.interruptible = false,
|
||||
.no_wait_gpu = false
|
||||
};
|
||||
size_t max_segment;
|
||||
|
||||
/* wtf swapping */
|
||||
if (bo->pages)
|
||||
|
|
@ -215,8 +216,13 @@ int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
|
|||
if (!bo->pages)
|
||||
goto out;
|
||||
|
||||
ret = sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0,
|
||||
nr_pages << PAGE_SHIFT, GFP_KERNEL);
|
||||
max_segment = virtio_max_dma_size(qdev->vdev);
|
||||
max_segment &= PAGE_MASK;
|
||||
if (max_segment > SCATTERLIST_MAX_SEGMENT)
|
||||
max_segment = SCATTERLIST_MAX_SEGMENT;
|
||||
ret = __sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0,
|
||||
nr_pages << PAGE_SHIFT,
|
||||
max_segment, GFP_KERNEL);
|
||||
if (ret)
|
||||
goto out;
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -790,7 +790,10 @@ static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
|
|||
|
||||
static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
|
||||
{
|
||||
u32 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
u32 val;
|
||||
|
||||
/* We do not support the SMBUS Quick command */
|
||||
val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||||
|
||||
if (adap->algo->reg_slave)
|
||||
val |= I2C_FUNC_SLAVE;
|
||||
|
|
|
|||
|
|
@ -94,6 +94,7 @@ static int i2c_dw_unreg_slave(struct i2c_client *slave)
|
|||
|
||||
dev->disable_int(dev);
|
||||
dev->disable(dev);
|
||||
synchronize_irq(dev->irq);
|
||||
dev->slave = NULL;
|
||||
pm_runtime_put(dev->dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -1194,19 +1194,28 @@ static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
|
|||
int i;
|
||||
|
||||
status = acpi_get_object_info(obj_handle, &info);
|
||||
if (!ACPI_SUCCESS(status) || !(info->valid & ACPI_VALID_HID))
|
||||
if (ACPI_FAILURE(status))
|
||||
return AE_OK;
|
||||
|
||||
if (!(info->valid & ACPI_VALID_HID))
|
||||
goto smo88xx_not_found;
|
||||
|
||||
hid = info->hardware_id.string;
|
||||
if (!hid)
|
||||
return AE_OK;
|
||||
goto smo88xx_not_found;
|
||||
|
||||
i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
|
||||
if (i < 0)
|
||||
return AE_OK;
|
||||
goto smo88xx_not_found;
|
||||
|
||||
kfree(info);
|
||||
|
||||
*((bool *)return_value) = true;
|
||||
return AE_CTRL_TERMINATE;
|
||||
|
||||
smo88xx_not_found:
|
||||
kfree(info);
|
||||
return AE_OK;
|
||||
}
|
||||
|
||||
static bool is_dell_system_with_lis3lv02d(void)
|
||||
|
|
|
|||
|
|
@ -234,6 +234,10 @@ static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
|
|||
.max_num_msgs = 255,
|
||||
};
|
||||
|
||||
static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
|
||||
.flags = I2C_AQ_NO_ZERO_LEN,
|
||||
};
|
||||
|
||||
static const struct mtk_i2c_compatible mt2712_compat = {
|
||||
.regs = mt_i2c_regs_v1,
|
||||
.pmic_i2c = 0,
|
||||
|
|
@ -298,6 +302,7 @@ static const struct mtk_i2c_compatible mt8173_compat = {
|
|||
};
|
||||
|
||||
static const struct mtk_i2c_compatible mt8183_compat = {
|
||||
.quirks = &mt8183_i2c_quirks,
|
||||
.regs = mt_i2c_regs_v2,
|
||||
.pmic_i2c = 0,
|
||||
.dcm = 0,
|
||||
|
|
@ -870,7 +875,11 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
|
|||
|
||||
static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
if (adap->quirks->flags & I2C_AQ_NO_ZERO_LEN)
|
||||
return I2C_FUNC_I2C |
|
||||
(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
||||
else
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm mtk_i2c_algorithm = {
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@
|
|||
#define SB800_PIIX4_PORT_IDX_MASK 0x06
|
||||
#define SB800_PIIX4_PORT_IDX_SHIFT 1
|
||||
|
||||
/* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
|
||||
/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
|
||||
#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
|
||||
#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
|
||||
#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
|
||||
|
|
@ -358,18 +358,16 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
|
|||
/* Find which register is used for port selection */
|
||||
if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
|
||||
PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
|
||||
switch (PIIX4_dev->device) {
|
||||
case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS:
|
||||
if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
|
||||
(PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
|
||||
PIIX4_dev->revision >= 0x1F)) {
|
||||
piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
|
||||
piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
|
||||
piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
|
||||
break;
|
||||
case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS:
|
||||
default:
|
||||
} else {
|
||||
piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
|
||||
piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
|
||||
piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
|
||||
|
|
|
|||
|
|
@ -832,7 +832,7 @@ EXPORT_SYMBOL_GPL(i2c_new_device);
|
|||
*/
|
||||
void i2c_unregister_device(struct i2c_client *client)
|
||||
{
|
||||
if (!client)
|
||||
if (IS_ERR_OR_NULL(client))
|
||||
return;
|
||||
|
||||
if (client->dev.of_node) {
|
||||
|
|
|
|||
|
|
@ -1962,6 +1962,10 @@ int siw_create_listen(struct iw_cm_id *id, int backlog)
|
|||
struct sockaddr_in s_laddr, *s_raddr;
|
||||
const struct in_ifaddr *ifa;
|
||||
|
||||
if (!in_dev) {
|
||||
rv = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
memcpy(&s_laddr, &id->local_addr, sizeof(s_laddr));
|
||||
s_raddr = (struct sockaddr_in *)&id->remote_addr;
|
||||
|
||||
|
|
@ -1991,22 +1995,27 @@ int siw_create_listen(struct iw_cm_id *id, int backlog)
|
|||
struct sockaddr_in6 *s_laddr = &to_sockaddr_in6(id->local_addr),
|
||||
*s_raddr = &to_sockaddr_in6(id->remote_addr);
|
||||
|
||||
if (!in6_dev) {
|
||||
rv = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
siw_dbg(id->device,
|
||||
"laddr %pI6:%d, raddr %pI6:%d\n",
|
||||
&s_laddr->sin6_addr, ntohs(s_laddr->sin6_port),
|
||||
&s_raddr->sin6_addr, ntohs(s_raddr->sin6_port));
|
||||
|
||||
read_lock_bh(&in6_dev->lock);
|
||||
rtnl_lock();
|
||||
list_for_each_entry(ifp, &in6_dev->addr_list, if_list) {
|
||||
struct sockaddr_in6 bind_addr;
|
||||
|
||||
if (ifp->flags & (IFA_F_TENTATIVE | IFA_F_DEPRECATED))
|
||||
continue;
|
||||
if (ipv6_addr_any(&s_laddr->sin6_addr) ||
|
||||
ipv6_addr_equal(&s_laddr->sin6_addr, &ifp->addr)) {
|
||||
bind_addr.sin6_family = AF_INET6;
|
||||
bind_addr.sin6_port = s_laddr->sin6_port;
|
||||
bind_addr.sin6_flowinfo = 0;
|
||||
bind_addr.sin6_addr = ifp->addr;
|
||||
bind_addr.sin6_scope_id = dev->ifindex;
|
||||
struct sockaddr_in6 bind_addr = {
|
||||
.sin6_family = AF_INET6,
|
||||
.sin6_port = s_laddr->sin6_port,
|
||||
.sin6_flowinfo = 0,
|
||||
.sin6_addr = ifp->addr,
|
||||
.sin6_scope_id = dev->ifindex };
|
||||
|
||||
rv = siw_listen_address(id, backlog,
|
||||
(struct sockaddr *)&bind_addr,
|
||||
|
|
@ -2015,12 +2024,12 @@ int siw_create_listen(struct iw_cm_id *id, int backlog)
|
|||
listeners++;
|
||||
}
|
||||
}
|
||||
read_unlock_bh(&in6_dev->lock);
|
||||
|
||||
rtnl_unlock();
|
||||
in6_dev_put(in6_dev);
|
||||
} else {
|
||||
return -EAFNOSUPPORT;
|
||||
rv = -EAFNOSUPPORT;
|
||||
}
|
||||
out:
|
||||
if (listeners)
|
||||
rv = 0;
|
||||
else if (!rv)
|
||||
|
|
|
|||
|
|
@ -729,7 +729,7 @@ static int rk808_remove(struct i2c_client *client)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int rk8xx_suspend(struct device *dev)
|
||||
static int __maybe_unused rk8xx_suspend(struct device *dev)
|
||||
{
|
||||
struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
int ret = 0;
|
||||
|
|
@ -749,7 +749,7 @@ static int rk8xx_suspend(struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int rk8xx_resume(struct device *dev)
|
||||
static int __maybe_unused rk8xx_resume(struct device *dev)
|
||||
{
|
||||
struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
int ret = 0;
|
||||
|
|
@ -768,7 +768,7 @@ static int rk8xx_resume(struct device *dev)
|
|||
|
||||
return ret;
|
||||
}
|
||||
SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume);
|
||||
static SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume);
|
||||
|
||||
static struct i2c_driver rk808_i2c_driver = {
|
||||
.driver = {
|
||||
|
|
|
|||
|
|
@ -1292,6 +1292,12 @@ int mmc_attach_sd(struct mmc_host *host)
|
|||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Some SD cards claims an out of spec VDD voltage range. Let's treat
|
||||
* these bits as being in-valid and especially also bit7.
|
||||
*/
|
||||
ocr &= ~0x7FFF;
|
||||
|
||||
rocr = mmc_select_voltage(host, ocr);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -369,6 +369,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
|
|||
host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
|
||||
host->mmc_host_ops.hs400_enhanced_strobe =
|
||||
sdhci_cdns_hs400_enhanced_strobe;
|
||||
sdhci_enable_v4_mode(host);
|
||||
|
||||
sdhci_get_of_property(pdev);
|
||||
|
||||
|
|
|
|||
|
|
@ -357,6 +357,9 @@ static int sdhci_at91_probe(struct platform_device *pdev)
|
|||
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
|
||||
/* HS200 is broken at this moment */
|
||||
host->quirks2 = SDHCI_QUIRK2_BROKEN_HS200;
|
||||
|
||||
ret = sdhci_add_host(host);
|
||||
if (ret)
|
||||
goto pm_runtime_disable;
|
||||
|
|
|
|||
|
|
@ -217,10 +217,11 @@ static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
|
|||
struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
|
||||
u32 div, val, mask;
|
||||
|
||||
div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
|
||||
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
|
||||
|
||||
clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
|
||||
sdhci_enable_clk(host, clk);
|
||||
div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
|
||||
div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
|
||||
sdhci_enable_clk(host, div);
|
||||
|
||||
/* enable auto gate sdhc_enable_auto_gate */
|
||||
val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
|
||||
|
|
@ -373,6 +374,11 @@ static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
|
|||
return 1 << 31;
|
||||
}
|
||||
|
||||
static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sdhci_ops sdhci_sprd_ops = {
|
||||
.read_l = sdhci_sprd_readl,
|
||||
.write_l = sdhci_sprd_writel,
|
||||
|
|
@ -385,6 +391,7 @@ static struct sdhci_ops sdhci_sprd_ops = {
|
|||
.set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
|
||||
.hw_reset = sdhci_sprd_hw_reset,
|
||||
.get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
|
||||
.get_ro = sdhci_sprd_get_ro,
|
||||
};
|
||||
|
||||
static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
||||
|
|
@ -501,9 +508,12 @@ static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
|
|||
}
|
||||
|
||||
static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
|
||||
.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
|
||||
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
|
||||
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
||||
SDHCI_QUIRK_MISSING_CAPS,
|
||||
.quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
|
||||
SDHCI_QUIRK2_USE_32BIT_BLK_CNT,
|
||||
SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
|
||||
SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
||||
.ops = &sdhci_sprd_ops,
|
||||
};
|
||||
|
||||
|
|
@ -605,6 +615,16 @@ static int sdhci_sprd_probe(struct platform_device *pdev)
|
|||
|
||||
sdhci_enable_v4_mode(host);
|
||||
|
||||
/*
|
||||
* Supply the existing CAPS, but clear the UHS-I modes. This
|
||||
* will allow these modes to be specified only by device
|
||||
* tree properties through mmc_of_parse().
|
||||
*/
|
||||
host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
|
||||
host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
|
||||
host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
|
||||
SDHCI_SUPPORT_DDR50);
|
||||
|
||||
ret = sdhci_setup_host(host);
|
||||
if (ret)
|
||||
goto pm_runtime_disable;
|
||||
|
|
|
|||
|
|
@ -258,6 +258,16 @@ static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
|
|||
}
|
||||
}
|
||||
|
||||
static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
|
||||
{
|
||||
/*
|
||||
* Write-enable shall be assumed if GPIO is missing in a board's
|
||||
* device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
|
||||
* Tegra.
|
||||
*/
|
||||
return mmc_gpio_get_ro(host->mmc);
|
||||
}
|
||||
|
||||
static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
|
||||
{
|
||||
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
||||
|
|
@ -1224,6 +1234,7 @@ static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
|
|||
};
|
||||
|
||||
static const struct sdhci_ops tegra_sdhci_ops = {
|
||||
.get_ro = tegra_sdhci_get_ro,
|
||||
.read_w = tegra_sdhci_readw,
|
||||
.write_l = tegra_sdhci_writel,
|
||||
.set_clock = tegra_sdhci_set_clock,
|
||||
|
|
@ -1279,6 +1290,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
|
|||
};
|
||||
|
||||
static const struct sdhci_ops tegra114_sdhci_ops = {
|
||||
.get_ro = tegra_sdhci_get_ro,
|
||||
.read_w = tegra_sdhci_readw,
|
||||
.write_w = tegra_sdhci_writew,
|
||||
.write_l = tegra_sdhci_writel,
|
||||
|
|
@ -1332,6 +1344,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
|
|||
};
|
||||
|
||||
static const struct sdhci_ops tegra210_sdhci_ops = {
|
||||
.get_ro = tegra_sdhci_get_ro,
|
||||
.read_w = tegra_sdhci_readw,
|
||||
.write_w = tegra210_sdhci_writew,
|
||||
.write_l = tegra_sdhci_writel,
|
||||
|
|
@ -1366,6 +1379,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
|
|||
};
|
||||
|
||||
static const struct sdhci_ops tegra186_sdhci_ops = {
|
||||
.get_ro = tegra_sdhci_get_ro,
|
||||
.read_w = tegra_sdhci_readw,
|
||||
.write_l = tegra_sdhci_writel,
|
||||
.set_clock = tegra_sdhci_set_clock,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
menuconfig MTD_HYPERBUS
|
||||
tristate "HyperBus support"
|
||||
depends on HAS_IOMEM
|
||||
select MTD_CFI
|
||||
select MTD_MAP_BANK_WIDTH_2
|
||||
select MTD_CFI_AMDSTD
|
||||
|
|
|
|||
|
|
@ -478,6 +478,7 @@ static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
|
|||
unsigned long *supported,
|
||||
struct phylink_link_state *state)
|
||||
{
|
||||
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
||||
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
|
||||
|
||||
if (!phy_interface_mode_is_rgmii(state->interface) &&
|
||||
|
|
@ -487,8 +488,10 @@ static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
|
|||
state->interface != PHY_INTERFACE_MODE_INTERNAL &&
|
||||
state->interface != PHY_INTERFACE_MODE_MOCA) {
|
||||
bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
|
||||
dev_err(ds->dev,
|
||||
"Unsupported interface: %d\n", state->interface);
|
||||
if (port != core_readl(priv, CORE_IMP0_PRT_ID))
|
||||
dev_err(ds->dev,
|
||||
"Unsupported interface: %d for port %d\n",
|
||||
state->interface, port);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -526,6 +529,9 @@ static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
|
|||
u32 id_mode_dis = 0, port_mode;
|
||||
u32 reg, offset;
|
||||
|
||||
if (port == core_readl(priv, CORE_IMP0_PRT_ID))
|
||||
return;
|
||||
|
||||
if (priv->type == BCM7445_DEVICE_ID)
|
||||
offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ static void gve_get_stats(struct net_device *dev, struct rtnl_link_stats64 *s)
|
|||
u64_stats_fetch_begin(&priv->tx[ring].statss);
|
||||
s->tx_packets += priv->tx[ring].pkt_done;
|
||||
s->tx_bytes += priv->tx[ring].bytes_done;
|
||||
} while (u64_stats_fetch_retry(&priv->rx[ring].statss,
|
||||
} while (u64_stats_fetch_retry(&priv->tx[ring].statss,
|
||||
start));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -109,13 +109,15 @@ build_progress_params(struct mlx5e_tx_wqe *wqe, u16 pc, u32 sqn,
|
|||
|
||||
static void tx_fill_wi(struct mlx5e_txqsq *sq,
|
||||
u16 pi, u8 num_wqebbs,
|
||||
skb_frag_t *resync_dump_frag)
|
||||
skb_frag_t *resync_dump_frag,
|
||||
u32 num_bytes)
|
||||
{
|
||||
struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
|
||||
|
||||
wi->skb = NULL;
|
||||
wi->num_wqebbs = num_wqebbs;
|
||||
wi->resync_dump_frag = resync_dump_frag;
|
||||
wi->num_bytes = num_bytes;
|
||||
}
|
||||
|
||||
void mlx5e_ktls_tx_offload_set_pending(struct mlx5e_ktls_offload_context_tx *priv_tx)
|
||||
|
|
@ -143,7 +145,7 @@ post_static_params(struct mlx5e_txqsq *sq,
|
|||
|
||||
umr_wqe = mlx5e_sq_fetch_wqe(sq, MLX5E_KTLS_STATIC_UMR_WQE_SZ, &pi);
|
||||
build_static_params(umr_wqe, sq->pc, sq->sqn, priv_tx, fence);
|
||||
tx_fill_wi(sq, pi, MLX5E_KTLS_STATIC_WQEBBS, NULL);
|
||||
tx_fill_wi(sq, pi, MLX5E_KTLS_STATIC_WQEBBS, NULL, 0);
|
||||
sq->pc += MLX5E_KTLS_STATIC_WQEBBS;
|
||||
}
|
||||
|
||||
|
|
@ -157,7 +159,7 @@ post_progress_params(struct mlx5e_txqsq *sq,
|
|||
|
||||
wqe = mlx5e_sq_fetch_wqe(sq, MLX5E_KTLS_PROGRESS_WQE_SZ, &pi);
|
||||
build_progress_params(wqe, sq->pc, sq->sqn, priv_tx, fence);
|
||||
tx_fill_wi(sq, pi, MLX5E_KTLS_PROGRESS_WQEBBS, NULL);
|
||||
tx_fill_wi(sq, pi, MLX5E_KTLS_PROGRESS_WQEBBS, NULL, 0);
|
||||
sq->pc += MLX5E_KTLS_PROGRESS_WQEBBS;
|
||||
}
|
||||
|
||||
|
|
@ -248,43 +250,37 @@ tx_post_resync_params(struct mlx5e_txqsq *sq,
|
|||
mlx5e_ktls_tx_post_param_wqes(sq, priv_tx, skip_static_post, true);
|
||||
}
|
||||
|
||||
struct mlx5e_dump_wqe {
|
||||
struct mlx5_wqe_ctrl_seg ctrl;
|
||||
struct mlx5_wqe_data_seg data;
|
||||
};
|
||||
|
||||
static int
|
||||
tx_post_resync_dump(struct mlx5e_txqsq *sq, struct sk_buff *skb,
|
||||
skb_frag_t *frag, u32 tisn, bool first)
|
||||
{
|
||||
struct mlx5_wqe_ctrl_seg *cseg;
|
||||
struct mlx5_wqe_eth_seg *eseg;
|
||||
struct mlx5_wqe_data_seg *dseg;
|
||||
struct mlx5e_tx_wqe *wqe;
|
||||
struct mlx5e_dump_wqe *wqe;
|
||||
dma_addr_t dma_addr = 0;
|
||||
u16 ds_cnt, ds_cnt_inl;
|
||||
u8 num_wqebbs;
|
||||
u16 pi, ihs;
|
||||
u16 ds_cnt;
|
||||
int fsz;
|
||||
|
||||
ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
|
||||
ihs = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
|
||||
ds_cnt_inl = DIV_ROUND_UP(ihs - INL_HDR_START_SZ, MLX5_SEND_WQE_DS);
|
||||
ds_cnt += ds_cnt_inl;
|
||||
ds_cnt += 1; /* one frag */
|
||||
u16 pi;
|
||||
|
||||
wqe = mlx5e_sq_fetch_wqe(sq, sizeof(*wqe), &pi);
|
||||
|
||||
ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
|
||||
num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
|
||||
|
||||
cseg = &wqe->ctrl;
|
||||
eseg = &wqe->eth;
|
||||
dseg = wqe->data;
|
||||
dseg = &wqe->data;
|
||||
|
||||
cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_DUMP);
|
||||
cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
|
||||
cseg->tisn = cpu_to_be32(tisn << 8);
|
||||
cseg->fm_ce_se = first ? MLX5_FENCE_MODE_INITIATOR_SMALL : 0;
|
||||
|
||||
eseg->inline_hdr.sz = cpu_to_be16(ihs);
|
||||
memcpy(eseg->inline_hdr.start, skb->data, ihs);
|
||||
dseg += ds_cnt_inl;
|
||||
|
||||
fsz = skb_frag_size(frag);
|
||||
dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
|
||||
DMA_TO_DEVICE);
|
||||
|
|
@ -296,7 +292,7 @@ tx_post_resync_dump(struct mlx5e_txqsq *sq, struct sk_buff *skb,
|
|||
dseg->byte_count = cpu_to_be32(fsz);
|
||||
mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
|
||||
|
||||
tx_fill_wi(sq, pi, num_wqebbs, frag);
|
||||
tx_fill_wi(sq, pi, num_wqebbs, frag, fsz);
|
||||
sq->pc += num_wqebbs;
|
||||
|
||||
WARN(num_wqebbs > MLX5E_KTLS_MAX_DUMP_WQEBBS,
|
||||
|
|
@ -323,7 +319,7 @@ static void tx_post_fence_nop(struct mlx5e_txqsq *sq)
|
|||
struct mlx5_wq_cyc *wq = &sq->wq;
|
||||
u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
|
||||
|
||||
tx_fill_wi(sq, pi, 1, NULL);
|
||||
tx_fill_wi(sq, pi, 1, NULL, 0);
|
||||
|
||||
mlx5e_post_nop_fence(wq, sq->sqn, &sq->pc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -590,7 +590,8 @@ mlx5_fw_fatal_reporter_dump(struct devlink_health_reporter *reporter,
|
|||
data_size = crdump_size - offset;
|
||||
else
|
||||
data_size = MLX5_CR_DUMP_CHUNK_SIZE;
|
||||
err = devlink_fmsg_binary_put(fmsg, cr_data, data_size);
|
||||
err = devlink_fmsg_binary_put(fmsg, (char *)cr_data + offset,
|
||||
data_size);
|
||||
if (err)
|
||||
goto free_data;
|
||||
}
|
||||
|
|
@ -700,6 +701,16 @@ static void poll_health(struct timer_list *t)
|
|||
if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
|
||||
goto out;
|
||||
|
||||
fatal_error = check_fatal_sensors(dev);
|
||||
|
||||
if (fatal_error && !health->fatal_error) {
|
||||
mlx5_core_err(dev, "Fatal error %u detected\n", fatal_error);
|
||||
dev->priv.health.fatal_error = fatal_error;
|
||||
print_health_info(dev);
|
||||
mlx5_trigger_health_work(dev);
|
||||
goto out;
|
||||
}
|
||||
|
||||
count = ioread32be(health->health_counter);
|
||||
if (count == health->prev)
|
||||
++health->miss_counter;
|
||||
|
|
@ -718,15 +729,6 @@ static void poll_health(struct timer_list *t)
|
|||
if (health->synd && health->synd != prev_synd)
|
||||
queue_work(health->wq, &health->report_work);
|
||||
|
||||
fatal_error = check_fatal_sensors(dev);
|
||||
|
||||
if (fatal_error && !health->fatal_error) {
|
||||
mlx5_core_err(dev, "Fatal error %u detected\n", fatal_error);
|
||||
dev->priv.health.fatal_error = fatal_error;
|
||||
print_health_info(dev);
|
||||
mlx5_trigger_health_work(dev);
|
||||
}
|
||||
|
||||
out:
|
||||
mod_timer(&health->timer, get_next_poll_jiffies());
|
||||
}
|
||||
|
|
|
|||
|
|
@ -317,7 +317,7 @@ static void is2_action_set(struct vcap_data *data,
|
|||
break;
|
||||
case OCELOT_ACL_ACTION_TRAP:
|
||||
VCAP_ACT_SET(PORT_MASK, 0x0);
|
||||
VCAP_ACT_SET(MASK_MODE, 0x0);
|
||||
VCAP_ACT_SET(MASK_MODE, 0x1);
|
||||
VCAP_ACT_SET(POLICE_ENA, 0x0);
|
||||
VCAP_ACT_SET(POLICE_IDX, 0x0);
|
||||
VCAP_ACT_SET(CPU_QU_NUM, 0x0);
|
||||
|
|
|
|||
|
|
@ -1416,6 +1416,13 @@ nfp_flower_setup_indr_tc_block(struct net_device *netdev, struct nfp_app *app,
|
|||
|
||||
switch (f->command) {
|
||||
case FLOW_BLOCK_BIND:
|
||||
cb_priv = nfp_flower_indr_block_cb_priv_lookup(app, netdev);
|
||||
if (cb_priv &&
|
||||
flow_block_cb_is_busy(nfp_flower_setup_indr_block_cb,
|
||||
cb_priv,
|
||||
&nfp_block_cb_list))
|
||||
return -EBUSY;
|
||||
|
||||
cb_priv = kmalloc(sizeof(*cb_priv), GFP_KERNEL);
|
||||
if (!cb_priv)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -1325,7 +1325,7 @@ static int qed_slowpath_start(struct qed_dev *cdev,
|
|||
&drv_version);
|
||||
if (rc) {
|
||||
DP_NOTICE(cdev, "Failed sending drv version command\n");
|
||||
return rc;
|
||||
goto err4;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1333,6 +1333,8 @@ static int qed_slowpath_start(struct qed_dev *cdev,
|
|||
|
||||
return 0;
|
||||
|
||||
err4:
|
||||
qed_ll2_dealloc_if(cdev);
|
||||
err3:
|
||||
qed_hw_stop(cdev);
|
||||
err2:
|
||||
|
|
|
|||
|
|
@ -5921,6 +5921,7 @@ static struct sk_buff *rtl8169_try_rx_copy(void *data,
|
|||
skb = napi_alloc_skb(&tp->napi, pkt_size);
|
||||
if (skb)
|
||||
skb_copy_to_linear_data(skb, data, pkt_size);
|
||||
dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
|
||||
|
||||
return skb;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2775,6 +2775,7 @@ static int cpsw_probe(struct platform_device *pdev)
|
|||
if (!cpsw)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, cpsw);
|
||||
cpsw->dev = dev;
|
||||
|
||||
mode = devm_gpiod_get_array_optional(dev, "mode", GPIOD_OUT_LOW);
|
||||
|
|
@ -2879,7 +2880,6 @@ static int cpsw_probe(struct platform_device *pdev)
|
|||
goto clean_cpts;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, cpsw);
|
||||
priv = netdev_priv(ndev);
|
||||
priv->cpsw = cpsw;
|
||||
priv->ndev = ndev;
|
||||
|
|
|
|||
|
|
@ -802,7 +802,7 @@ static int hwsim_add_one(struct genl_info *info, struct device *dev,
|
|||
err = hwsim_subscribe_all_others(phy);
|
||||
if (err < 0) {
|
||||
mutex_unlock(&hwsim_phys_lock);
|
||||
goto err_reg;
|
||||
goto err_subscribe;
|
||||
}
|
||||
}
|
||||
list_add_tail(&phy->list, &hwsim_phys);
|
||||
|
|
@ -812,6 +812,8 @@ static int hwsim_add_one(struct genl_info *info, struct device *dev,
|
|||
|
||||
return idx;
|
||||
|
||||
err_subscribe:
|
||||
ieee802154_unregister_hw(phy->hw);
|
||||
err_reg:
|
||||
kfree(pib);
|
||||
err_pib:
|
||||
|
|
@ -901,9 +903,9 @@ static __init int hwsim_init_module(void)
|
|||
return 0;
|
||||
|
||||
platform_drv:
|
||||
genl_unregister_family(&hwsim_genl_family);
|
||||
platform_dev:
|
||||
platform_device_unregister(mac802154hwsim_dev);
|
||||
platform_dev:
|
||||
genl_unregister_family(&hwsim_genl_family);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue