ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>hifive-unleashed-5.1
Joseph Lo
Stephen Warren
parent
731a927438
commit
e9f624499c
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@ -33,6 +33,7 @@ obj-$(CONFIG_TEGRA_PCI) += pcie.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
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endif
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@ -239,6 +239,12 @@
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#define TEGRA_KFUSE_BASE 0x7000FC00
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#define TEGRA_KFUSE_SIZE SZ_1K
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#define TEGRA_EMC0_BASE 0x7001A000
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#define TEGRA_EMC0_SIZE SZ_2K
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#define TEGRA_EMC1_BASE 0x7001A800
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#define TEGRA_EMC1_SIZE SZ_2K
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#define TEGRA_CSITE_BASE 0x70040000
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#define TEGRA_CSITE_SIZE SZ_256K
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@ -215,7 +215,9 @@ static bool tegra_lp1_iram_hook(void)
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tegra20_lp1_iram_hook();
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break;
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case TEGRA30:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
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case TEGRA114:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
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tegra30_lp1_iram_hook();
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break;
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default:
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@ -241,7 +243,9 @@ static bool tegra_sleep_core_init(void)
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tegra20_sleep_core_init();
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break;
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case TEGRA30:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
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case TEGRA114:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
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tegra30_sleep_core_init();
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break;
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default:
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@ -65,6 +65,10 @@
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#define CLK_RESET_PLLA_MISC 0xbc
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#define CLK_RESET_PLLX_BASE 0xe0
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#define CLK_RESET_PLLX_MISC 0xe4
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#define CLK_RESET_PLLX_MISC3 0x518
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#define CLK_RESET_PLLX_MISC3_IDDQ 3
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#define CLK_RESET_PLLM_MISC_IDDQ 5
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#define CLK_RESET_PLLC_MISC_IDDQ 26
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#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
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@ -114,6 +118,18 @@
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beq 1b
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.endm
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.macro pll_iddq_exit, rd, car, iddq, iddq_bit
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ldr \rd, [\car, #\iddq]
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bic \rd, \rd, #(1<<\iddq_bit)
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str \rd, [\car, #\iddq]
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.endm
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.macro pll_iddq_entry, rd, car, iddq, iddq_bit
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ldr \rd, [\car, #\iddq]
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orr \rd, \rd, #(1<<\iddq_bit)
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str \rd, [\car, #\iddq]
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.endm
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra30_hotplug_shutdown(void)
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@ -315,6 +331,32 @@ ENTRY(tegra30_lp1_reset)
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str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
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str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
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cmp r10, #TEGRA30
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beq _no_pll_iddq_exit
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pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
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pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
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pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
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mov32 r7, TEGRA_TMRUS_BASE
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ldr r1, [r7]
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add r1, r1, #2
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wait_until r1, r7, r3
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/* enable PLLM via PMC */
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mov32 r2, TEGRA_PMC_BASE
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ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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orr r1, r1, #(1 << 12)
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str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
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b _pll_m_c_x_done
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_no_pll_iddq_exit:
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/* enable PLLM via PMC */
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mov32 r2, TEGRA_PMC_BASE
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ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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@ -322,11 +364,13 @@ ENTRY(tegra30_lp1_reset)
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str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
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pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
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pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
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_pll_m_c_x_done:
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
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pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
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pll_locked r1, r0, CLK_RESET_PLLM_BASE
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pll_locked r1, r0, CLK_RESET_PLLP_BASE
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pll_locked r1, r0, CLK_RESET_PLLA_BASE
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@ -346,7 +390,11 @@ ENTRY(tegra30_lp1_reset)
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ldr r4, [r5, #0x1C] @ restore SCLK_BURST
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str r4, [r0, #CLK_RESET_SCLK_BURST]
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mov32 r4, ((1 << 28) | (0x8)) @ burst policy is PLLX
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cmp r10, #TEGRA30
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movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
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movteq r4, #:upper16:((1 << 28) | (0x8))
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movwne r4, #:lower16:((1 << 28) | (0xe))
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movtne r4, #:upper16:((1 << 28) | (0xe))
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str r4, [r0, #CLK_RESET_CCLK_BURST]
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/* Restore pad power state to normal */
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@ -356,8 +404,13 @@ ENTRY(tegra30_lp1_reset)
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orr r1, r1, #(1 << 30)
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str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
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mov32 r0, TEGRA_EMC_BASE @ r0 reserved for emc base
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cmp r10, #TEGRA30
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movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
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movteq r0, #:upper16:TEGRA_EMC_BASE
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movwne r0, #:lower16:TEGRA_EMC0_BASE
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movtne r0, #:upper16:TEGRA_EMC0_BASE
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exit_self_refresh:
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ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
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str r1, [r0, #EMC_XM2VTTGENPADCTRL]
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ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
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@ -372,8 +425,14 @@ ENTRY(tegra30_lp1_reset)
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emc_timing_update r1, r0
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cmp r10, #TEGRA114
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movweq r1, #:lower16:TEGRA_EMC1_BASE
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movteq r1, #:upper16:TEGRA_EMC1_BASE
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cmpeq r0, r1
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ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
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orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
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orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
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str r1, [r0, #EMC_AUTO_CAL_CONFIG]
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emc_wait_auto_cal_onetime:
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@ -388,9 +447,10 @@ emc_wait_auto_cal_onetime:
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mov r1, #0
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str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
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mov r1, #1
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str r1, [r0, #EMC_NOP]
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str r1, [r0, #EMC_NOP]
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str r1, [r0, #EMC_REFRESH]
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cmp r10, #TEGRA30
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streq r1, [r0, #EMC_NOP]
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streq r1, [r0, #EMC_NOP]
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streq r1, [r0, #EMC_REFRESH]
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emc_device_mask r1, r0
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@ -452,6 +512,16 @@ zcal_done:
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ldr r1, [r5, #0x0] @ restore EMC_CFG
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str r1, [r0, #EMC_CFG]
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/* Tegra114 had dual EMC channel, now config the other one */
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cmp r10, #TEGRA114
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bne __no_dual_emc_chanl
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mov32 r1, TEGRA_EMC1_BASE
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cmp r0, r1
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movne r0, r1
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addne r5, r5, #0x20
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bne exit_self_refresh
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__no_dual_emc_chanl:
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mov32 r0, TEGRA_PMC_BASE
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ldr r0, [r0, #PMC_SCRATCH41]
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mov pc, r0 @ jump to tegra_resume
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@ -468,12 +538,30 @@ tegra30_sdram_pad_address:
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
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tegra114_sdram_pad_address:
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.word TEGRA_EMC0_BASE + EMC_CFG @0x0
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.word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
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.word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
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.word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
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.word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
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.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
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.word TEGRA_EMC1_BASE + EMC_CFG @0x20
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.word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
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.word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
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tegra30_sdram_pad_size:
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.word tegra30_sdram_pad_size - tegra30_sdram_pad_address
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.word tegra114_sdram_pad_address - tegra30_sdram_pad_address
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tegra114_sdram_pad_size:
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.word tegra30_sdram_pad_size - tegra114_sdram_pad_address
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.type tegra30_sdram_pad_save, %object
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tegra30_sdram_pad_save:
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.rept (tegra30_sdram_pad_size - tegra30_sdram_pad_address) / 4
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.rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
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.long 0
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.endr
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@ -497,6 +585,7 @@ tegra30_tear_down_core:
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* r5 = TEGRA_CLK_RESET_BASE
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* r6 = TEGRA_FLOW_CTRL_BASE
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* r7 = TEGRA_TMRUS_BASE
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* r10= SoC ID
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*/
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tegra30_switch_cpu_to_clk32k:
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/*
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@ -543,6 +632,11 @@ tegra30_switch_cpu_to_clk32k:
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bic r0, r0, #(1 << 30)
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str r0, [r5, #CLK_RESET_PLLX_BASE]
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cmp r10, #TEGRA30
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beq _no_pll_in_iddq
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pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
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_no_pll_in_iddq:
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/* switch to CLKS */
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mov r0, #0 /* brust policy = 32KHz */
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str r0, [r5, #CLK_RESET_SCLK_BURST]
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@ -594,14 +688,19 @@ halted:
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* r5 = TEGRA_CLK_RESET_BASE
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* r6 = TEGRA_FLOW_CTRL_BASE
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* r7 = TEGRA_TMRUS_BASE
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* r10= SoC ID
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*/
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tegra30_sdram_self_refresh:
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adr r2, tegra30_sdram_pad_address
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adr r8, tegra30_sdram_pad_save
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
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cmp r10, #TEGRA30
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adreq r2, tegra30_sdram_pad_address
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ldreq r3, tegra30_sdram_pad_size
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adrne r2, tegra114_sdram_pad_address
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ldrne r3, tegra114_sdram_pad_size
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mov r9, #0
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ldr r3, tegra30_sdram_pad_size
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padsave:
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ldr r0, [r2, r9] @ r0 is the addr in the pad_address
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@ -615,13 +714,18 @@ padsave_done:
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dsb
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mov32 r0, TEGRA_EMC_BASE @ r0 reserved for emc base addr
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cmp r10, #TEGRA30
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ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
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ldrne r0, =TEGRA_EMC0_BASE
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enter_self_refresh:
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cmp r10, #TEGRA30
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mov r1, #0
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str r1, [r0, #EMC_ZCAL_INTERVAL]
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str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
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ldr r1, [r0, #EMC_CFG]
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bic r1, r1, #(1 << 28)
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bicne r1, r1, #(1 << 29)
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str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
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emc_timing_update r1, r0
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@ -660,11 +764,22 @@ emcself:
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and r1, r1, r2
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str r1, [r0, #EMC_XM2VTTGENPADCTRL]
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ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
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orr r1, r1, #7 @ set E_NO_VTTGEN
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cmp r10, #TEGRA30
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orreq r1, r1, #7 @ set E_NO_VTTGEN
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orrne r1, r1, #0x3f
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str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
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emc_timing_update r1, r0
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/* Tegra114 had dual EMC channel, now config the other one */
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cmp r10, #TEGRA114
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bne no_dual_emc_chanl
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mov32 r1, TEGRA_EMC1_BASE
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cmp r0, r1
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movne r0, r1
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bne enter_self_refresh
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no_dual_emc_chanl:
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ldr r1, [r4, #PMC_CTRL]
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tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
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bne pmc_io_dpd_skip
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