mtd: s3c2410: make ecc mode configurable via platform data
Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode field in the drivers's platform data structure so it can be selectable via platform data. Also setting this field to NAND_ECC_SOFT in all boards using this driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled. Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>hifive-unleashed-5.1
parent
6685924924
commit
e9f66ae23c
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@ -171,6 +171,7 @@ static struct s3c2410_platform_nand smdk_nand_info = {
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.twrph1 = 20,
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.twrph1 = 20,
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.nr_sets = ARRAY_SIZE(smdk_nand_sets),
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.nr_sets = ARRAY_SIZE(smdk_nand_sets),
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.sets = smdk_nand_sets,
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.sets = smdk_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* devices we initialise */
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/* devices we initialise */
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@ -223,6 +223,7 @@ static struct s3c2410_platform_nand __initdata anubis_nand_info = {
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.nr_sets = ARRAY_SIZE(anubis_nand_sets),
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.nr_sets = ARRAY_SIZE(anubis_nand_sets),
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.sets = anubis_nand_sets,
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.sets = anubis_nand_sets,
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.select_chip = anubis_nand_select,
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.select_chip = anubis_nand_select,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* IDE channels */
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/* IDE channels */
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@ -114,6 +114,7 @@ static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
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.twrph1 = 40,
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.twrph1 = 40,
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.nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
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.nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
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.sets = at2440evb_nand_sets,
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.sets = at2440evb_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* DM9000AEP 10/100 ethernet controller */
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/* DM9000AEP 10/100 ethernet controller */
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@ -299,6 +299,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
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.nr_sets = ARRAY_SIZE(bast_nand_sets),
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.nr_sets = ARRAY_SIZE(bast_nand_sets),
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.sets = bast_nand_sets,
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.sets = bast_nand_sets,
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.select_chip = bast_nand_select,
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.select_chip = bast_nand_select,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* DM9000 */
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/* DM9000 */
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@ -443,6 +443,7 @@ static struct s3c2410_platform_nand __initdata gta02_nand_info = {
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.twrph1 = 15,
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.twrph1 = 15,
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.nr_sets = ARRAY_SIZE(gta02_nand_sets),
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.nr_sets = ARRAY_SIZE(gta02_nand_sets),
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.sets = gta02_nand_sets,
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.sets = gta02_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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@ -232,6 +232,7 @@ static struct s3c2410_platform_nand __initdata jive_nand_info = {
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.twrph1 = 40,
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.twrph1 = 40,
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.sets = jive_nand_sets,
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.sets = jive_nand_sets,
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.nr_sets = ARRAY_SIZE(jive_nand_sets),
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.nr_sets = ARRAY_SIZE(jive_nand_sets),
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static int __init jive_mtdset(char *options)
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static int __init jive_mtdset(char *options)
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@ -287,6 +287,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
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.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
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.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
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.sets = mini2440_nand_sets,
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.sets = mini2440_nand_sets,
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.ignore_unset_ecc = 1,
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.ignore_unset_ecc = 1,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* DM9000AEP 10/100 ethernet controller */
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/* DM9000AEP 10/100 ethernet controller */
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@ -238,6 +238,7 @@ static struct s3c2410_platform_nand __initdata osiris_nand_info = {
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.nr_sets = ARRAY_SIZE(osiris_nand_sets),
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.nr_sets = ARRAY_SIZE(osiris_nand_sets),
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.sets = osiris_nand_sets,
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.sets = osiris_nand_sets,
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.select_chip = osiris_nand_select,
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.select_chip = osiris_nand_select,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* PCMCIA control and configuration */
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/* PCMCIA control and configuration */
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@ -284,6 +284,7 @@ static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
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.twrph1 = 20,
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.twrph1 = 20,
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.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
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.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
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.sets = qt2410_nand_sets,
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.sets = qt2410_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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/* UDC */
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/* UDC */
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@ -611,6 +611,7 @@ static struct s3c2410_platform_nand rx1950_nand_info = {
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.twrph1 = 15,
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.twrph1 = 15,
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.nr_sets = ARRAY_SIZE(rx1950_nand_sets),
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.nr_sets = ARRAY_SIZE(rx1950_nand_sets),
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.sets = rx1950_nand_sets,
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.sets = rx1950_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
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static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
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@ -164,6 +164,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
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.twrph1 = 15,
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.twrph1 = 15,
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.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
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.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
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.sets = rx3715_nand_sets,
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.sets = rx3715_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static struct platform_device *rx3715_devices[] __initdata = {
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static struct platform_device *rx3715_devices[] __initdata = {
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@ -117,6 +117,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = {
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.twrph1 = 20,
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.twrph1 = 20,
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.nr_sets = ARRAY_SIZE(vstms_nand_sets),
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.nr_sets = ARRAY_SIZE(vstms_nand_sets),
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.sets = vstms_nand_sets,
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.sets = vstms_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static struct platform_device *vstms_devices[] __initdata = {
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static struct platform_device *vstms_devices[] __initdata = {
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@ -204,6 +204,7 @@ static struct s3c2410_platform_nand hmt_nand_info = {
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.twrph1 = 40,
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.twrph1 = 40,
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.nr_sets = ARRAY_SIZE(hmt_nand_sets),
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.nr_sets = ARRAY_SIZE(hmt_nand_sets),
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.sets = hmt_nand_sets,
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.sets = hmt_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static struct gpio_led hmt_leds[] = {
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static struct gpio_led hmt_leds[] = {
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@ -142,6 +142,7 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
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.twrph1 = 40,
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.twrph1 = 40,
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.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
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.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
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.sets = mini6410_nand_sets,
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.sets = mini6410_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
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static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
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@ -194,6 +194,7 @@ static struct s3c2410_platform_nand real6410_nand_info = {
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.twrph1 = 40,
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.twrph1 = 40,
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.nr_sets = ARRAY_SIZE(real6410_nand_sets),
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.nr_sets = ARRAY_SIZE(real6410_nand_sets),
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.sets = real6410_nand_sets,
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.sets = real6410_nand_sets,
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.ecc_mode = NAND_ECC_SOFT,
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};
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};
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static struct platform_device *real6410_devices[] __initdata = {
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static struct platform_device *real6410_devices[] __initdata = {
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@ -179,15 +179,6 @@ config MTD_NAND_S3C2410_DEBUG
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help
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help
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Enable debugging of the S3C NAND driver
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Enable debugging of the S3C NAND driver
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config MTD_NAND_S3C2410_HWECC
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bool "Samsung S3C NAND Hardware ECC"
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depends on MTD_NAND_S3C2410
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help
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Enable the use of the controller's internal ECC generator when
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using NAND. Early versions of the chips have had problems with
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incorrect ECC generation, and if using these, the default of
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software ECC is preferable.
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config MTD_NAND_NDFC
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config MTD_NAND_NDFC
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tristate "NDFC NanD Flash Controller"
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tristate "NDFC NanD Flash Controller"
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depends on 4xx
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depends on 4xx
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@ -497,7 +497,6 @@ static int s3c2412_nand_devready(struct mtd_info *mtd)
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/* ECC handling functions */
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/* ECC handling functions */
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#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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u_char *read_ecc, u_char *calc_ecc)
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{
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{
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@ -649,7 +648,6 @@ static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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return 0;
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return 0;
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}
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}
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#endif
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/* over-ride the standard functions for a little more speed. We can
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/* over-ride the standard functions for a little more speed. We can
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* use read/write block to move the data buffers to/from the controller
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* use read/write block to move the data buffers to/from the controller
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@ -858,50 +856,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
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nmtd->info = info;
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nmtd->info = info;
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nmtd->set = set;
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nmtd->set = set;
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#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
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chip->ecc.mode = info->platform->ecc_mode;
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chip->ecc.calculate = s3c2410_nand_calculate_ecc;
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chip->ecc.correct = s3c2410_nand_correct_data;
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.strength = 1;
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
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chip->ecc.calculate = s3c2410_nand_calculate_ecc;
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break;
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case TYPE_S3C2412:
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chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
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chip->ecc.calculate = s3c2412_nand_calculate_ecc;
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break;
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case TYPE_S3C2440:
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chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
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chip->ecc.calculate = s3c2440_nand_calculate_ecc;
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break;
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}
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#else
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->ecc.algo = NAND_ECC_HAMMING;
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#endif
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if (set->disable_ecc)
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chip->ecc.mode = NAND_ECC_NONE;
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switch (chip->ecc.mode) {
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case NAND_ECC_NONE:
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dev_info(info->device, "NAND ECC disabled\n");
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break;
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case NAND_ECC_SOFT:
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dev_info(info->device, "NAND soft ECC\n");
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break;
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case NAND_ECC_HW:
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dev_info(info->device, "NAND hardware ECC\n");
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break;
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default:
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dev_info(info->device, "NAND ECC UNKNOWN\n");
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break;
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}
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/* If you use u-boot BBT creation code, specifying this flag will
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/* If you use u-boot BBT creation code, specifying this flag will
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* let the kernel fish out the BBT from the NAND, and also skip the
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* let the kernel fish out the BBT from the NAND, and also skip the
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@ -923,28 +878,74 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
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*
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*
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* The internal state is currently limited to the ECC state information.
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* The internal state is currently limited to the ECC state information.
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*/
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*/
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static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
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static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
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struct s3c2410_nand_mtd *nmtd)
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struct s3c2410_nand_mtd *nmtd)
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{
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{
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struct nand_chip *chip = &nmtd->chip;
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struct nand_chip *chip = &nmtd->chip;
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dev_dbg(info->device, "chip %p => page shift %d\n",
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switch (chip->ecc.mode) {
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chip, chip->page_shift);
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if (chip->ecc.mode != NAND_ECC_HW)
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case NAND_ECC_NONE:
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return;
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dev_info(info->device, "ECC disabled\n");
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break;
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case NAND_ECC_SOFT:
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/*
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* This driver expects Hamming based ECC when ecc_mode is set
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* to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
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* avoid adding an extra ecc_algo field to
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* s3c2410_platform_nand.
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*/
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chip->ecc.algo = NAND_ECC_HAMMING;
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dev_info(info->device, "soft ECC\n");
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break;
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case NAND_ECC_HW:
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chip->ecc.calculate = s3c2410_nand_calculate_ecc;
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chip->ecc.correct = s3c2410_nand_correct_data;
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chip->ecc.strength = 1;
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
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chip->ecc.calculate = s3c2410_nand_calculate_ecc;
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break;
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case TYPE_S3C2412:
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chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
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chip->ecc.calculate = s3c2412_nand_calculate_ecc;
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break;
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case TYPE_S3C2440:
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chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
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chip->ecc.calculate = s3c2440_nand_calculate_ecc;
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break;
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}
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dev_dbg(info->device, "chip %p => page shift %d\n",
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chip, chip->page_shift);
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/* change the behaviour depending on whether we are using
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/* change the behaviour depending on whether we are using
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* the large or small page nand device */
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* the large or small page nand device */
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if (chip->page_shift > 10) {
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chip->ecc.size = 256;
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chip->ecc.bytes = 3;
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} else {
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chip->ecc.size = 512;
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chip->ecc.bytes = 3;
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mtd_set_ooblayout(nand_to_mtd(chip),
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&s3c2410_ooblayout_ops);
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}
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if (chip->page_shift > 10) {
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dev_info(info->device, "hardware ECC\n");
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chip->ecc.size = 256;
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break;
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chip->ecc.bytes = 3;
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} else {
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default:
|
||||||
chip->ecc.size = 512;
|
dev_err(info->device, "invalid ECC mode!\n");
|
||||||
chip->ecc.bytes = 3;
|
return -EINVAL;
|
||||||
mtd_set_ooblayout(nand_to_mtd(chip), &s3c2410_ooblayout_ops);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* s3c24xx_nand_probe
|
/* s3c24xx_nand_probe
|
||||||
|
@ -1046,7 +1047,9 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
|
||||||
NULL);
|
NULL);
|
||||||
|
|
||||||
if (nmtd->scan_res == 0) {
|
if (nmtd->scan_res == 0) {
|
||||||
s3c2410_nand_update_chip(info, nmtd);
|
err = s3c2410_nand_update_chip(info, nmtd);
|
||||||
|
if (err < 0)
|
||||||
|
goto exit_error;
|
||||||
nand_scan_tail(mtd);
|
nand_scan_tail(mtd);
|
||||||
s3c2410_nand_add_partition(info, nmtd, sets);
|
s3c2410_nand_add_partition(info, nmtd, sets);
|
||||||
}
|
}
|
||||||
|
|
|
@ -12,9 +12,10 @@
|
||||||
#ifndef __MTD_NAND_S3C2410_H
|
#ifndef __MTD_NAND_S3C2410_H
|
||||||
#define __MTD_NAND_S3C2410_H
|
#define __MTD_NAND_S3C2410_H
|
||||||
|
|
||||||
|
#include <linux/mtd/nand.h>
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct s3c2410_nand_set - define a set of one or more nand chips
|
* struct s3c2410_nand_set - define a set of one or more nand chips
|
||||||
* @disable_ecc: Entirely disable ECC - Dangerous
|
|
||||||
* @flash_bbt: Openmoko u-boot can create a Bad Block Table
|
* @flash_bbt: Openmoko u-boot can create a Bad Block Table
|
||||||
* Setting this flag will allow the kernel to
|
* Setting this flag will allow the kernel to
|
||||||
* look for it at boot time and also skip the NAND
|
* look for it at boot time and also skip the NAND
|
||||||
|
@ -31,7 +32,6 @@
|
||||||
* a warning at boot time.
|
* a warning at boot time.
|
||||||
*/
|
*/
|
||||||
struct s3c2410_nand_set {
|
struct s3c2410_nand_set {
|
||||||
unsigned int disable_ecc:1;
|
|
||||||
unsigned int flash_bbt:1;
|
unsigned int flash_bbt:1;
|
||||||
|
|
||||||
unsigned int options;
|
unsigned int options;
|
||||||
|
@ -51,6 +51,8 @@ struct s3c2410_platform_nand {
|
||||||
|
|
||||||
unsigned int ignore_unset_ecc:1;
|
unsigned int ignore_unset_ecc:1;
|
||||||
|
|
||||||
|
nand_ecc_modes_t ecc_mode;
|
||||||
|
|
||||||
int nr_sets;
|
int nr_sets;
|
||||||
struct s3c2410_nand_set *sets;
|
struct s3c2410_nand_set *sets;
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue