Merge branch 'pci/host-tegra' into next
* pci/host-tegra: PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs PCI: tegra: Stop setting pcibios_min_mem PCI: tegra: Use generic pci_remap_iospace() rather than ARM32-specific one PCI: tegra: Use lower-case hex consistently for register definitions Conflicts: drivers/pci/host/pci-tegra.c Drop stray pci_ioremap_io() per Thierry Reding <treding@nvidia.com>; removal tested by Jon Hunter <jonathanh@nvidia.com>.hifive-unleashed-5.1
Bjorn Helgaas
commit
ea1f4e9d1d
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@ -185,26 +185,26 @@
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#define AFI_PEXBIAS_CTRL_0 0x168
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#define RP_VEND_XP 0x00000F00
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#define RP_VEND_XP 0x00000f00
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#define RP_VEND_XP_DL_UP (1 << 30)
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#define RP_PRIV_MISC 0x00000FE0
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#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
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#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
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#define RP_PRIV_MISC 0x00000fe0
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#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
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#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
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#define RP_LINK_CONTROL_STATUS 0x00000090
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#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
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#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
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#define PADS_CTL_SEL 0x0000009C
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#define PADS_CTL_SEL 0x0000009c
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#define PADS_CTL 0x000000A0
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#define PADS_CTL 0x000000a0
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#define PADS_CTL_IDDQ_1L (1 << 0)
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#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
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#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
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#define PADS_PLL_CTL_TEGRA20 0x000000B8
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#define PADS_PLL_CTL_TEGRA30 0x000000B4
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#define PADS_PLL_CTL_TEGRA20 0x000000b8
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#define PADS_PLL_CTL_TEGRA30 0x000000b4
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#define PADS_PLL_CTL_RST_B4SM (1 << 1)
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#define PADS_PLL_CTL_LOCKDET (1 << 8)
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#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
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@ -216,9 +216,9 @@
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#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
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#define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
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#define PADS_REFCLK_CFG0 0x000000C8
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#define PADS_REFCLK_CFG1 0x000000CC
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#define PADS_REFCLK_BIAS 0x000000D0
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#define PADS_REFCLK_CFG0 0x000000c8
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#define PADS_REFCLK_CFG1 0x000000cc
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#define PADS_REFCLK_BIAS 0x000000d0
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/*
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* Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
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@ -230,15 +230,6 @@
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#define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
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#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
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/* Default value provided by HW engineering is 0xfa5c */
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#define PADS_REFCLK_CFG_VALUE \
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( \
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(0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
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(0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
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(0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
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(0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
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)
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struct tegra_msi {
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struct msi_controller chip;
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DECLARE_BITMAP(used, INT_PCI_MSI_NR);
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@ -254,6 +245,8 @@ struct tegra_pcie_soc_data {
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unsigned int msi_base_shift;
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u32 pads_pll_ctl;
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u32 tx_ref_sel;
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u32 pads_refclk_cfg0;
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u32 pads_refclk_cfg1;
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bool has_pex_clkreq_en;
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bool has_pex_bias_ctrl;
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bool has_intr_prsnt_sense;
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@ -628,8 +621,6 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
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if (err < 0)
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return err;
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pci_ioremap_io(pcie->pio.start, pcie->io.start);
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pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);
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pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &pcie->prefetch,
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@ -640,6 +631,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
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if (err < 0)
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return err;
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pci_remap_iospace(&pcie->pio, pcie->io.start);
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return 1;
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}
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@ -831,12 +823,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
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value |= PADS_PLL_CTL_RST_B4SM;
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pads_writel(pcie, value, soc->pads_pll_ctl);
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/* Configure the reference clock driver */
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value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
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pads_writel(pcie, value, PADS_REFCLK_CFG0);
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if (soc->num_ports > 2)
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pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
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/* wait for the PLL to lock */
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err = tegra_pcie_pll_wait(pcie, 500);
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if (err < 0) {
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@ -920,6 +906,7 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
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static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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struct tegra_pcie_port *port;
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int err;
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@ -945,6 +932,12 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
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}
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}
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/* Configure the reference clock driver */
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pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
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if (soc->num_ports > 2)
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pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
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return 0;
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}
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@ -2055,6 +2048,7 @@ static const struct tegra_pcie_soc_data tegra20_pcie_data = {
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.msi_base_shift = 0,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
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.pads_refclk_cfg0 = 0xfa5cfa5c,
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.has_pex_clkreq_en = false,
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.has_pex_bias_ctrl = false,
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.has_intr_prsnt_sense = false,
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@ -2067,6 +2061,8 @@ static const struct tegra_pcie_soc_data tegra30_pcie_data = {
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.msi_base_shift = 8,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.pads_refclk_cfg0 = 0xfa5cfa5c,
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.pads_refclk_cfg1 = 0xfa5cfa5c,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_intr_prsnt_sense = true,
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@ -2079,6 +2075,7 @@ static const struct tegra_pcie_soc_data tegra124_pcie_data = {
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.msi_base_shift = 8,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.pads_refclk_cfg0 = 0x44ac44ac,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_intr_prsnt_sense = true,
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@ -2225,8 +2222,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
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if (err < 0)
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return err;
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pcibios_min_mem = 0;
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err = tegra_pcie_get_resources(pcie);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to request resources: %d\n", err);
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