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MIPS: Honor L2 bypass bit 

On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates
that the L2 cache is disabled and therefore Linux should not attempt
to use it.

[Ralf: Moved the code added by Kevin's original patch into a separate
function that can easily be replaced for platforms that need more a
different probe.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>
Patchwork: https://patchwork.linux-mips.org/patch/1723/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Kevin Cernekee 2010-10-20 20:05:42 -07:00 committed by Ralf Baechle
parent af23117263
commit ea31a6b203
1 changed files with 30 additions and 4 deletions
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34
arch/mips/mm/sc-mips.c
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@ -57,6 +57,34 @@ static struct bcache_ops mips_sc_ops = {
.bc_inv = mips_sc_inv
};
/*
* Check if the L2 cache controller is activated on a particular platform.
* MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
* cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
* cache being disabled. However there is no guarantee for this to be
* true on all platforms. In an act of stupidity the spec defined bits
* 12..15 as implementation defined so below function will eventually have
* to be replaced by a platform specific probe.
*/
static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
{
/* Check the bypass bit (L2B) */
switch (c->cputype) {
case CPU_34K:
case CPU_74K:
case CPU_1004K:
case CPU_BMIPS5000:
if (config2 & (1 << 12))
return 0;
}
tmp = (config2 >> 4) & 0x0f;
if (0 < tmp && tmp <= 7)
c->scache.linesz = 2 << tmp;
else
return 0;
}
static inline int __init mips_sc_probe(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
@ -79,10 +107,8 @@ static inline int __init mips_sc_probe(void)
return 0;
config2 = read_c0_config2();
tmp = (config2 >> 4) & 0x0f;
if (0 < tmp && tmp <= 7)
c->scache.linesz = 2 << tmp;
else
if (!mips_sc_is_activated(c))
return 0;
tmp = (config2 >> 8) & 0x0f;