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ARM64: dts: enable pcie on imx8mm 

Enable PCIe on iMX8MM platforms.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Richard Zhu 2019-08-20 04:23:49 -04:00 committed by Dong Aisheng
parent 30aeb21a6f
commit ea334b7f64
2 changed files with 68 additions and 1 deletions
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28
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
View File

@ -36,6 +36,12 @@
#reset-cells = <0>;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -104,6 +110,20 @@
};
};
&pcie0{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
ext_osc = <1>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -448,6 +468,14 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41

41
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -221,6 +222,7 @@
domain-index = <1>;
domain-name = "pcie";
parent-domains = <&hsiomix_pd>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
};
usb_otg1_pd: usbotg1-pd {
@ -584,13 +586,19 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
pcie_phy: pcie-phy@302f0000 {
compatible = "fsl,imx7d-pcie-phy";
reg = <0x302f0000 0x10000>;
status = "disabled";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mm-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@ -1111,6 +1119,37 @@
status = "disabled";
};
pcie0: pcie@33800000 {
compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
reg = <0x33800000 0x400000>,
<0x1ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
power-domains = <&pcie_pd>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */