raid5: add AVX optimized RAID5 checksumming
Optimize RAID5 xor checksumming by taking advantage of 256-bit YMM registers introduced in AVX. Signed-off-by: Jim Kukunas <james.t.kukunas@linux.intel.com> Signed-off-by: NeilBrown <neilb@suse.de>hifive-unleashed-5.1
Jim Kukunas
NeilBrown
parent
56a519913e
commit
ea4d26ae24
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@ -115,9 +115,10 @@ cfi-sections := $(call as-instr,.cfi_sections .debug_frame,-DCONFIG_AS_CFI_SECTI
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# does binutils support specific instructions?
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asinstr := $(call as-instr,fxsaveq (%rax),-DCONFIG_AS_FXSAVEQ=1)
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avx_instr := $(call as-instr,vxorps %ymm0$(comma)%ymm1$(comma)%ymm2,-DCONFIG_AS_AVX=1)
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KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr)
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KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr)
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KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr)
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KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr)
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LDFLAGS := -m elf_$(UTS_MACHINE)
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@ -861,6 +861,9 @@ static struct xor_block_template xor_block_pIII_sse = {
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.do_5 = xor_sse_5,
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};
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/* Also try the AVX routines */
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#include "xor_avx.h"
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/* Also try the generic routines. */
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#include <asm-generic/xor.h>
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@ -871,6 +874,7 @@ do { \
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xor_speed(&xor_block_8regs_p); \
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xor_speed(&xor_block_32regs); \
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xor_speed(&xor_block_32regs_p); \
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AVX_XOR_SPEED; \
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if (cpu_has_xmm) \
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xor_speed(&xor_block_pIII_sse); \
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if (cpu_has_mmx) { \
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@ -883,6 +887,6 @@ do { \
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
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AVX_SELECT(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
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#endif /* _ASM_X86_XOR_32_H */
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@ -347,15 +347,21 @@ static struct xor_block_template xor_block_sse = {
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.do_5 = xor_sse_5,
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};
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/* Also try the AVX routines */
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#include "xor_avx.h"
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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AVX_XOR_SPEED; \
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xor_speed(&xor_block_sse); \
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} while (0)
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/* We force the use of the SSE xor block because it can write around L2.
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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AVX_SELECT(&xor_block_sse)
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#endif /* _ASM_X86_XOR_64_H */
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@ -0,0 +1,214 @@
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#ifndef _ASM_X86_XOR_AVX_H
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#define _ASM_X86_XOR_AVX_H
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/*
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* Optimized RAID-5 checksumming functions for AVX
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*
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* Copyright (C) 2012 Intel Corporation
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* Author: Jim Kukunas <james.t.kukunas@linux.intel.com>
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*
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* Based on Ingo Molnar and Zach Brown's respective MMX and SSE routines
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifdef CONFIG_AS_AVX
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#include <linux/compiler.h>
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#include <asm/i387.h>
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#define ALIGN32 __aligned(32)
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#define YMM_SAVED_REGS 4
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#define YMMS_SAVE \
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do { \
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preempt_disable(); \
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cr0 = read_cr0(); \
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clts(); \
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asm volatile("vmovaps %%ymm0, %0" : "=m" (ymm_save[0]) : : "memory"); \
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asm volatile("vmovaps %%ymm1, %0" : "=m" (ymm_save[32]) : : "memory"); \
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asm volatile("vmovaps %%ymm2, %0" : "=m" (ymm_save[64]) : : "memory"); \
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asm volatile("vmovaps %%ymm3, %0" : "=m" (ymm_save[96]) : : "memory"); \
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} while (0);
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#define YMMS_RESTORE \
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do { \
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asm volatile("sfence" : : : "memory"); \
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asm volatile("vmovaps %0, %%ymm3" : : "m" (ymm_save[96])); \
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asm volatile("vmovaps %0, %%ymm2" : : "m" (ymm_save[64])); \
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asm volatile("vmovaps %0, %%ymm1" : : "m" (ymm_save[32])); \
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asm volatile("vmovaps %0, %%ymm0" : : "m" (ymm_save[0])); \
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write_cr0(cr0); \
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preempt_enable(); \
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} while (0);
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#define BLOCK4(i) \
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BLOCK(32 * i, 0) \
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BLOCK(32 * (i + 1), 1) \
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BLOCK(32 * (i + 2), 2) \
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BLOCK(32 * (i + 3), 3)
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#define BLOCK16() \
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BLOCK4(0) \
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BLOCK4(4) \
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BLOCK4(8) \
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BLOCK4(12)
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static void xor_avx_2(unsigned long bytes, unsigned long *p0, unsigned long *p1)
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{
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unsigned long cr0, lines = bytes >> 9;
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char ymm_save[32 * YMM_SAVED_REGS] ALIGN32;
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YMMS_SAVE
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while (lines--) {
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#undef BLOCK
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#define BLOCK(i, reg) \
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do { \
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asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p0[i / sizeof(*p0)])); \
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asm volatile("vmovdqa %%ymm" #reg ", %0" : \
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"=m" (p0[i / sizeof(*p0)])); \
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} while (0);
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BLOCK16()
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p0 = (unsigned long *)((uintptr_t)p0 + 512);
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p1 = (unsigned long *)((uintptr_t)p1 + 512);
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}
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YMMS_RESTORE
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}
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static void xor_avx_3(unsigned long bytes, unsigned long *p0, unsigned long *p1,
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unsigned long *p2)
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{
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unsigned long cr0, lines = bytes >> 9;
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char ymm_save[32 * YMM_SAVED_REGS] ALIGN32;
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YMMS_SAVE
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while (lines--) {
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#undef BLOCK
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#define BLOCK(i, reg) \
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do { \
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asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p1[i / sizeof(*p1)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p0[i / sizeof(*p0)])); \
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asm volatile("vmovdqa %%ymm" #reg ", %0" : \
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"=m" (p0[i / sizeof(*p0)])); \
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} while (0);
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BLOCK16()
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p0 = (unsigned long *)((uintptr_t)p0 + 512);
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p1 = (unsigned long *)((uintptr_t)p1 + 512);
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p2 = (unsigned long *)((uintptr_t)p2 + 512);
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}
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YMMS_RESTORE
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}
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static void xor_avx_4(unsigned long bytes, unsigned long *p0, unsigned long *p1,
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unsigned long *p2, unsigned long *p3)
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{
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unsigned long cr0, lines = bytes >> 9;
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char ymm_save[32 * YMM_SAVED_REGS] ALIGN32;
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YMMS_SAVE
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while (lines--) {
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#undef BLOCK
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#define BLOCK(i, reg) \
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do { \
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asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p3[i / sizeof(*p3)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p2[i / sizeof(*p2)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p1[i / sizeof(*p1)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p0[i / sizeof(*p0)])); \
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asm volatile("vmovdqa %%ymm" #reg ", %0" : \
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"=m" (p0[i / sizeof(*p0)])); \
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} while (0);
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BLOCK16();
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p0 = (unsigned long *)((uintptr_t)p0 + 512);
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p1 = (unsigned long *)((uintptr_t)p1 + 512);
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p2 = (unsigned long *)((uintptr_t)p2 + 512);
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p3 = (unsigned long *)((uintptr_t)p3 + 512);
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}
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YMMS_RESTORE
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}
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static void xor_avx_5(unsigned long bytes, unsigned long *p0, unsigned long *p1,
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unsigned long *p2, unsigned long *p3, unsigned long *p4)
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{
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unsigned long cr0, lines = bytes >> 9;
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char ymm_save[32 * YMM_SAVED_REGS] ALIGN32;
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YMMS_SAVE
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while (lines--) {
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#undef BLOCK
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#define BLOCK(i, reg) \
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do { \
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asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p4[i / sizeof(*p4)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p3[i / sizeof(*p3)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p2[i / sizeof(*p2)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p1[i / sizeof(*p1)])); \
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asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
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"m" (p0[i / sizeof(*p0)])); \
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asm volatile("vmovdqa %%ymm" #reg ", %0" : \
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"=m" (p0[i / sizeof(*p0)])); \
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} while (0);
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BLOCK16()
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p0 = (unsigned long *)((uintptr_t)p0 + 512);
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p1 = (unsigned long *)((uintptr_t)p1 + 512);
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p2 = (unsigned long *)((uintptr_t)p2 + 512);
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p3 = (unsigned long *)((uintptr_t)p3 + 512);
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p4 = (unsigned long *)((uintptr_t)p4 + 512);
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}
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YMMS_RESTORE
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}
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static struct xor_block_template xor_block_avx = {
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.name = "avx",
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.do_2 = xor_avx_2,
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.do_3 = xor_avx_3,
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.do_4 = xor_avx_4,
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.do_5 = xor_avx_5,
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};
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#define AVX_XOR_SPEED \
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do { \
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if (cpu_has_avx) \
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xor_speed(&xor_block_avx); \
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} while (0)
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#define AVX_SELECT(FASTEST) \
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(cpu_has_avx ? &xor_block_avx : FASTEST)
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#else
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#define AVX_XOR_SPEED {}
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#define AVX_SELECT(FASTEST) (FASTEST)
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#endif
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#endif
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