drm/nv04: Context switching fixes.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Francisco Jerez
Dave Airlie
parent
a5027ccd3c
commit
ea911a1cf4
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@ -28,6 +28,10 @@
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#include "nouveau_drv.h"
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static uint32_t nv04_graph_ctx_regs[] = {
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0x0040053c,
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0x00400544,
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0x00400540,
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0x00400548,
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NV04_PGRAPH_CTX_SWITCH1,
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NV04_PGRAPH_CTX_SWITCH2,
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NV04_PGRAPH_CTX_SWITCH3,
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@ -102,69 +106,69 @@ static uint32_t nv04_graph_ctx_regs[] = {
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NV04_PGRAPH_PATT_COLOR0,
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NV04_PGRAPH_PATT_COLOR1,
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NV04_PGRAPH_PATT_COLORRAM+0x00,
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NV04_PGRAPH_PATT_COLORRAM+0x01,
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NV04_PGRAPH_PATT_COLORRAM+0x02,
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NV04_PGRAPH_PATT_COLORRAM+0x03,
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NV04_PGRAPH_PATT_COLORRAM+0x04,
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NV04_PGRAPH_PATT_COLORRAM+0x05,
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NV04_PGRAPH_PATT_COLORRAM+0x06,
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NV04_PGRAPH_PATT_COLORRAM+0x07,
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NV04_PGRAPH_PATT_COLORRAM+0x08,
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NV04_PGRAPH_PATT_COLORRAM+0x09,
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NV04_PGRAPH_PATT_COLORRAM+0x0A,
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NV04_PGRAPH_PATT_COLORRAM+0x0B,
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NV04_PGRAPH_PATT_COLORRAM+0x0C,
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NV04_PGRAPH_PATT_COLORRAM+0x0D,
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NV04_PGRAPH_PATT_COLORRAM+0x0E,
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NV04_PGRAPH_PATT_COLORRAM+0x0F,
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NV04_PGRAPH_PATT_COLORRAM+0x0c,
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NV04_PGRAPH_PATT_COLORRAM+0x10,
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NV04_PGRAPH_PATT_COLORRAM+0x11,
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NV04_PGRAPH_PATT_COLORRAM+0x12,
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NV04_PGRAPH_PATT_COLORRAM+0x13,
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NV04_PGRAPH_PATT_COLORRAM+0x14,
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NV04_PGRAPH_PATT_COLORRAM+0x15,
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NV04_PGRAPH_PATT_COLORRAM+0x16,
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NV04_PGRAPH_PATT_COLORRAM+0x17,
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NV04_PGRAPH_PATT_COLORRAM+0x18,
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NV04_PGRAPH_PATT_COLORRAM+0x19,
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NV04_PGRAPH_PATT_COLORRAM+0x1A,
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NV04_PGRAPH_PATT_COLORRAM+0x1B,
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NV04_PGRAPH_PATT_COLORRAM+0x1C,
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NV04_PGRAPH_PATT_COLORRAM+0x1D,
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NV04_PGRAPH_PATT_COLORRAM+0x1E,
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NV04_PGRAPH_PATT_COLORRAM+0x1F,
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NV04_PGRAPH_PATT_COLORRAM+0x1c,
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NV04_PGRAPH_PATT_COLORRAM+0x20,
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NV04_PGRAPH_PATT_COLORRAM+0x21,
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NV04_PGRAPH_PATT_COLORRAM+0x22,
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NV04_PGRAPH_PATT_COLORRAM+0x23,
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NV04_PGRAPH_PATT_COLORRAM+0x24,
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NV04_PGRAPH_PATT_COLORRAM+0x25,
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NV04_PGRAPH_PATT_COLORRAM+0x26,
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NV04_PGRAPH_PATT_COLORRAM+0x27,
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NV04_PGRAPH_PATT_COLORRAM+0x28,
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NV04_PGRAPH_PATT_COLORRAM+0x29,
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NV04_PGRAPH_PATT_COLORRAM+0x2A,
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NV04_PGRAPH_PATT_COLORRAM+0x2B,
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NV04_PGRAPH_PATT_COLORRAM+0x2C,
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NV04_PGRAPH_PATT_COLORRAM+0x2D,
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NV04_PGRAPH_PATT_COLORRAM+0x2E,
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NV04_PGRAPH_PATT_COLORRAM+0x2F,
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NV04_PGRAPH_PATT_COLORRAM+0x2c,
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NV04_PGRAPH_PATT_COLORRAM+0x30,
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NV04_PGRAPH_PATT_COLORRAM+0x31,
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NV04_PGRAPH_PATT_COLORRAM+0x32,
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NV04_PGRAPH_PATT_COLORRAM+0x33,
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NV04_PGRAPH_PATT_COLORRAM+0x34,
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NV04_PGRAPH_PATT_COLORRAM+0x35,
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NV04_PGRAPH_PATT_COLORRAM+0x36,
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NV04_PGRAPH_PATT_COLORRAM+0x37,
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NV04_PGRAPH_PATT_COLORRAM+0x38,
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NV04_PGRAPH_PATT_COLORRAM+0x39,
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NV04_PGRAPH_PATT_COLORRAM+0x3A,
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NV04_PGRAPH_PATT_COLORRAM+0x3B,
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NV04_PGRAPH_PATT_COLORRAM+0x3C,
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NV04_PGRAPH_PATT_COLORRAM+0x3D,
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NV04_PGRAPH_PATT_COLORRAM+0x3E,
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NV04_PGRAPH_PATT_COLORRAM+0x3F,
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NV04_PGRAPH_PATT_COLORRAM+0x3c,
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NV04_PGRAPH_PATT_COLORRAM+0x40,
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NV04_PGRAPH_PATT_COLORRAM+0x44,
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NV04_PGRAPH_PATT_COLORRAM+0x48,
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NV04_PGRAPH_PATT_COLORRAM+0x4c,
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NV04_PGRAPH_PATT_COLORRAM+0x50,
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NV04_PGRAPH_PATT_COLORRAM+0x54,
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NV04_PGRAPH_PATT_COLORRAM+0x58,
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NV04_PGRAPH_PATT_COLORRAM+0x5c,
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NV04_PGRAPH_PATT_COLORRAM+0x60,
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NV04_PGRAPH_PATT_COLORRAM+0x64,
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NV04_PGRAPH_PATT_COLORRAM+0x68,
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NV04_PGRAPH_PATT_COLORRAM+0x6c,
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NV04_PGRAPH_PATT_COLORRAM+0x70,
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NV04_PGRAPH_PATT_COLORRAM+0x74,
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NV04_PGRAPH_PATT_COLORRAM+0x78,
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NV04_PGRAPH_PATT_COLORRAM+0x7c,
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NV04_PGRAPH_PATT_COLORRAM+0x80,
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NV04_PGRAPH_PATT_COLORRAM+0x84,
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NV04_PGRAPH_PATT_COLORRAM+0x88,
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NV04_PGRAPH_PATT_COLORRAM+0x8c,
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NV04_PGRAPH_PATT_COLORRAM+0x90,
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NV04_PGRAPH_PATT_COLORRAM+0x94,
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NV04_PGRAPH_PATT_COLORRAM+0x98,
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NV04_PGRAPH_PATT_COLORRAM+0x9c,
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NV04_PGRAPH_PATT_COLORRAM+0xa0,
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NV04_PGRAPH_PATT_COLORRAM+0xa4,
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NV04_PGRAPH_PATT_COLORRAM+0xa8,
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NV04_PGRAPH_PATT_COLORRAM+0xac,
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NV04_PGRAPH_PATT_COLORRAM+0xb0,
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NV04_PGRAPH_PATT_COLORRAM+0xb4,
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NV04_PGRAPH_PATT_COLORRAM+0xb8,
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NV04_PGRAPH_PATT_COLORRAM+0xbc,
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NV04_PGRAPH_PATT_COLORRAM+0xc0,
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NV04_PGRAPH_PATT_COLORRAM+0xc4,
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NV04_PGRAPH_PATT_COLORRAM+0xc8,
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NV04_PGRAPH_PATT_COLORRAM+0xcc,
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NV04_PGRAPH_PATT_COLORRAM+0xd0,
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NV04_PGRAPH_PATT_COLORRAM+0xd4,
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NV04_PGRAPH_PATT_COLORRAM+0xd8,
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NV04_PGRAPH_PATT_COLORRAM+0xdc,
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NV04_PGRAPH_PATT_COLORRAM+0xe0,
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NV04_PGRAPH_PATT_COLORRAM+0xe4,
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NV04_PGRAPH_PATT_COLORRAM+0xe8,
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NV04_PGRAPH_PATT_COLORRAM+0xec,
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NV04_PGRAPH_PATT_COLORRAM+0xf0,
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NV04_PGRAPH_PATT_COLORRAM+0xf4,
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NV04_PGRAPH_PATT_COLORRAM+0xf8,
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NV04_PGRAPH_PATT_COLORRAM+0xfc,
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NV04_PGRAPH_PATTERN,
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0x0040080c,
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NV04_PGRAPH_PATTERN_SHAPE,
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@ -247,14 +251,6 @@ static uint32_t nv04_graph_ctx_regs[] = {
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0x004004f8,
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0x0040047c,
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0x004004fc,
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0x0040053c,
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0x00400544,
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0x00400540,
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0x00400548,
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0x00400560,
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0x00400568,
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0x00400564,
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0x0040056c,
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0x00400534,
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0x00400538,
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0x00400514,
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@ -341,9 +337,8 @@ static uint32_t nv04_graph_ctx_regs[] = {
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0x00400500,
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0x00400504,
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NV04_PGRAPH_VALID1,
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NV04_PGRAPH_VALID2
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NV04_PGRAPH_VALID2,
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NV04_PGRAPH_DEBUG_3
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};
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struct graph_state {
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@ -388,6 +383,18 @@ nv04_graph_context_switch(struct drm_device *dev)
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pgraph->fifo_access(dev, true);
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}
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static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
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if (nv04_graph_ctx_regs[i] == reg)
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return &ctx->nv04[i];
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}
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return NULL;
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}
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int nv04_graph_create_context(struct nouveau_channel *chan)
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{
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struct graph_state *pgraph_ctx;
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@ -398,15 +405,8 @@ int nv04_graph_create_context(struct nouveau_channel *chan)
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if (pgraph_ctx == NULL)
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return -ENOMEM;
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/* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */
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pgraph_ctx->nv04[0] = 0x0001ffff;
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/* is it really needed ??? */
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#if 0
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dev_priv->fifos[channel].pgraph_ctx[1] =
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nv_rd32(dev, NV_PGRAPH_DEBUG_4);
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dev_priv->fifos[channel].pgraph_ctx[2] =
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nv_rd32(dev, 0x004006b0);
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#endif
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*ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
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return 0;
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}
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@ -429,9 +429,13 @@ int nv04_graph_load_context(struct nouveau_channel *chan)
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nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
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nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24);
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tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
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tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
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nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
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return 0;
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}
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@ -494,7 +498,7 @@ int nv04_graph_init(struct drm_device *dev)
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nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
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tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
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tmp |= dev_priv->engine.fifo.channels << 24;
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tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
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/* These don't belong here, they're part of a per-channel context */
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