From eb423eaee8410db4bcd4555b5080f3b7a6c73dd4 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 12 Apr 2017 14:45:53 +0800 Subject: [PATCH] MLK-14679-1: ARM: clk: spdif clock rate is too high for asrc spdif clock is one of the asrc clock source, which is used for ideal ratio mode. when set to 98.304MHz, it cause the divider of asrc input clock and output clock exceed the maximum value, and asrc driver saturate the value to maximum value, which will cause the ASRC's performance very bad. So we need to set spdif clock to a proper rate. which make asrc divider not exceed maximum value, at least one of divider not exceed maximum value. The target is spdif clock rate / output(or input) sample rate less than 1024(which is maximum divider). Reviewed-by: Viorel Suman Signed-off-by: Shengjiu Wang (cherry picked from commit 31c28c8fd66bfee7107f8161133cc8f97ea00a31) Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-imx6sx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index beed221ed4bd..274c31cf61a2 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -609,7 +609,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); - clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000); + clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 24576000); clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000);