powerpc: Always save/restore checkpointed regs during treclaim/trecheckpoint
Lazy save and restore of FP/Altivec means that a userspace process can be sent to userspace with FP or Altivec disabled and loaded only as required (by way of an FP/Altivec unavailable exception). Transactional Memory complicates this situation as a transaction could be started without FP/Altivec being loaded up. This causes the hardware to checkpoint incorrect registers. Handling FP/Altivec unavailable exceptions while a thread is transactional requires a reclaim and recheckpoint to ensure the CPU has correct state for both sets of registers. tm_reclaim() has optimisations to not always save the FP/Altivec registers to the checkpointed save area. This was originally done because the caller might have information that the checkpointed registers aren't valid due to lazy save and restore. We've also been a little vague as to how tm_reclaim() leaves the FP/Altivec state since it doesn't necessarily always save it to the thread struct. This has lead to an (incorrect) assumption that it leaves the checkpointed state on the CPU. tm_recheckpoint() has similar optimisations in reverse. It may not always reload the checkpointed FP/Altivec registers from the thread struct before the trecheckpoint. It is therefore quite unclear where it expects to get the state from. This didn't help with the assumption made about tm_reclaim(). These optimisations sit in what is by definition a slow path. If a process has to go through a reclaim/recheckpoint then its transaction will be doomed on returning to userspace. This mean that the process will be unable to complete its transaction and be forced to its failure handler. This is already an out if line case for userspace. Furthermore, the cost of copying 64 times 128 bits from registers isn't very long[0] (at all) on modern processors. As such it appears these optimisations have only served to increase code complexity and are unlikely to have had a measurable performance impact. Our transactional memory handling has been riddled with bugs. A cause of this has been difficulty in following the code flow, code complexity has not been our friend here. It makes sense to remove these optimisations in favour of a (hopefully) more stable implementation. This patch does mean that some times the assembly will needlessly save 'junk' registers which will subsequently get overwritten with the correct value by the C code which calls the assembly function. This small inefficiency is far outweighed by the reduction in complexity for general TM code, context switching paths, and transactional facility unavailable exception handler. 0: I tried to measure it once for other work and found that it was hiding in the noise of everything else I was working with. I find it exceedingly likely this will be the case here. Signed-off-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -11,10 +11,9 @@
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extern void tm_enable(void);
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extern void tm_reclaim(struct thread_struct *thread,
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unsigned long orig_msr, uint8_t cause);
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uint8_t cause);
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extern void tm_reclaim_current(uint8_t cause);
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extern void tm_recheckpoint(struct thread_struct *thread,
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unsigned long orig_msr);
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extern void tm_recheckpoint(struct thread_struct *thread);
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extern void tm_abort(uint8_t cause);
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extern void tm_save_sprs(struct thread_struct *thread);
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extern void tm_restore_sprs(struct thread_struct *thread);
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@ -876,6 +876,8 @@ static void tm_reclaim_thread(struct thread_struct *thr,
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giveup_all(container_of(thr, struct task_struct, thread));
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tm_reclaim(thr, cause);
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/*
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* If we are in a transaction and FP is off then we can't have
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* used FP inside that transaction. Hence the checkpointed
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@ -894,8 +896,6 @@ static void tm_reclaim_thread(struct thread_struct *thr,
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if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
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memcpy(&thr->ckvr_state, &thr->vr_state,
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sizeof(struct thread_vr_state));
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tm_reclaim(thr, thr->ckpt_regs.msr, cause);
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}
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void tm_reclaim_current(uint8_t cause)
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@ -946,11 +946,9 @@ out_and_saveregs:
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tm_save_sprs(thr);
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}
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extern void __tm_recheckpoint(struct thread_struct *thread,
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unsigned long orig_msr);
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extern void __tm_recheckpoint(struct thread_struct *thread);
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void tm_recheckpoint(struct thread_struct *thread,
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unsigned long orig_msr)
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void tm_recheckpoint(struct thread_struct *thread)
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{
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unsigned long flags;
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@ -969,15 +967,13 @@ void tm_recheckpoint(struct thread_struct *thread,
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*/
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tm_restore_sprs(thread);
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__tm_recheckpoint(thread, orig_msr);
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__tm_recheckpoint(thread);
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local_irq_restore(flags);
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}
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static inline void tm_recheckpoint_new_task(struct task_struct *new)
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{
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unsigned long msr;
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if (!cpu_has_feature(CPU_FTR_TM))
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return;
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@ -996,13 +992,11 @@ static inline void tm_recheckpoint_new_task(struct task_struct *new)
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tm_restore_sprs(&new->thread);
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return;
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}
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msr = new->thread.ckpt_regs.msr;
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/* Recheckpoint to restore original checkpointed register state. */
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TM_DEBUG("*** tm_recheckpoint of pid %d "
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"(new->msr 0x%lx, new->origmsr 0x%lx)\n",
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new->pid, new->thread.regs->msr, msr);
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TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
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new->pid, new->thread.regs->msr);
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tm_recheckpoint(&new->thread, msr);
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tm_recheckpoint(&new->thread);
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/*
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* The checkpointed state has been restored but the live state has
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@ -880,7 +880,7 @@ static long restore_tm_user_regs(struct pt_regs *regs,
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/* Make sure the transaction is marked as failed */
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current->thread.tm_texasr |= TEXASR_FS;
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/* This loads the checkpointed FP/VEC state, if used */
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tm_recheckpoint(¤t->thread, msr);
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tm_recheckpoint(¤t->thread);
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/* This loads the speculative FP/VEC state, if used */
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msr_check_and_set(msr & (MSR_FP | MSR_VEC));
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@ -552,7 +552,7 @@ static long restore_tm_sigcontexts(struct task_struct *tsk,
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/* Make sure the transaction is marked as failed */
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tsk->thread.tm_texasr |= TEXASR_FS;
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/* This loads the checkpointed FP/VEC state, if used */
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tm_recheckpoint(&tsk->thread, msr);
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tm_recheckpoint(&tsk->thread);
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msr_check_and_set(msr & (MSR_FP | MSR_VEC));
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if (msr & MSR_FP) {
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@ -79,15 +79,12 @@ _GLOBAL(tm_abort)
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blr
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/* void tm_reclaim(struct thread_struct *thread,
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* unsigned long orig_msr,
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* uint8_t cause)
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*
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* - Performs a full reclaim. This destroys outstanding
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* transactions and updates thread->regs.tm_ckpt_* with the
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* original checkpointed state. Note that thread->regs is
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* unchanged.
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* - FP regs are written back to thread->transact_fpr before
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* reclaiming. These are the transactional (current) versions.
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*
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* Purpose is to both abort transactions of, and preserve the state of,
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* a transactions at a context switch. We preserve/restore both sets of process
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@ -98,9 +95,9 @@ _GLOBAL(tm_abort)
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* Call with IRQs off, stacks get all out of sync for some periods in here!
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*/
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_GLOBAL(tm_reclaim)
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mfcr r6
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mfcr r5
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mflr r0
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stw r6, 8(r1)
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stw r5, 8(r1)
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std r0, 16(r1)
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std r2, STK_GOT(r1)
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stdu r1, -TM_FRAME_SIZE(r1)
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@ -108,7 +105,6 @@ _GLOBAL(tm_reclaim)
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/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
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std r3, STK_PARAM(R3)(r1)
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std r4, STK_PARAM(R4)(r1)
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SAVE_NVGPRS(r1)
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/* We need to setup MSR for VSX register save instructions. */
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@ -138,8 +134,8 @@ _GLOBAL(tm_reclaim)
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std r1, PACAR1(r13)
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/* Clear MSR RI since we are about to change r1, EE is already off. */
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li r4, 0
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mtmsrd r4, 1
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li r5, 0
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mtmsrd r5, 1
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/*
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* BE CAREFUL HERE:
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@ -151,7 +147,7 @@ _GLOBAL(tm_reclaim)
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* to user register state. (FPRs, CCR etc. also!)
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* Use an sprg and a tm_scratch in the PACA to shuffle.
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*/
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TRECLAIM(R5) /* Cause in r5 */
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TRECLAIM(R4) /* Cause in r4 */
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/* ******************** GPRs ******************** */
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/* Stash the checkpointed r13 away in the scratch SPR and get the real
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@ -242,40 +238,30 @@ _GLOBAL(tm_reclaim)
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/* ******************** FPR/VR/VSRs ************
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* After reclaiming, capture the checkpointed FPRs/VRs /if used/.
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*
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* (If VSX used, FP and VMX are implied. Or, we don't need to look
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* at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
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*
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* We're passed the thread's MSR as the second parameter
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* After reclaiming, capture the checkpointed FPRs/VRs.
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*
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* We enabled VEC/FP/VSX in the msr above, so we can execute these
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* instructions!
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*/
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ld r4, STK_PARAM(R4)(r1) /* Second parameter, MSR * */
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mr r3, r12
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andis. r0, r4, MSR_VEC@h
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beq dont_backup_vec
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/* Altivec (VEC/VMX/VR)*/
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addi r7, r3, THREAD_CKVRSTATE
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SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
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mfvscr v0
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li r6, VRSTATE_VSCR
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stvx v0, r7, r6
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dont_backup_vec:
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/* VRSAVE */
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mfspr r0, SPRN_VRSAVE
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std r0, THREAD_CKVRSAVE(r3)
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andi. r0, r4, MSR_FP
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beq dont_backup_fp
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/* Floating Point (FP) */
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addi r7, r3, THREAD_CKFPSTATE
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SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r7)
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dont_backup_fp:
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/* TM regs, incl TEXASR -- these live in thread_struct. Note they've
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* been updated by the treclaim, to explain to userland the failure
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*/
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subi r7, r7, STACK_FRAME_OVERHEAD
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/* We need to setup MSR for FP/VMX/VSX register save instructions. */
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mfmsr r6
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/* R4 = original MSR to indicate whether thread used FP/Vector etc. */
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/* Enable FP/vec in MSR if necessary! */
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lis r5, MSR_VEC@h
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mr r5, r6
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ori r5, r5, MSR_FP
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and. r5, r4, r5
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beq restore_gprs /* if neither, skip both */
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#ifdef CONFIG_ALTIVEC
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oris r5, r5, MSR_VEC@h
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#endif
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5, r5, MSR_VSX@h
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oris r5,r5, MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
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mtmsr r5
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mtmsrd r5
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#ifdef CONFIG_ALTIVEC
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/*
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* thread.fp_state[] version holds the 'live' (transactional)
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* and will be loaded subsequently by any FPUnavailable trap.
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*/
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andis. r0, r4, MSR_VEC@h
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beq dont_restore_vec
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addi r8, r3, THREAD_CKVRSTATE
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li r5, VRSTATE_VSCR
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lvx v0, r8, r5
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mtvscr v0
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REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
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dont_restore_vec:
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ld r5, THREAD_CKVRSAVE(r3)
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mtspr SPRN_VRSAVE, r5
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#endif
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andi. r0, r4, MSR_FP
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beq dont_restore_fp
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addi r8, r3, THREAD_CKFPSTATE
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lfd fr0, FPSTATE_FPSCR(r8)
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MTFSF_L(fr0)
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REST_32FPRS_VSRS(0, R4, R8)
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dont_restore_fp:
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mtmsr r6 /* FP/Vec off again! */
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restore_gprs:
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@ -1693,7 +1693,7 @@ void fp_unavailable_tm(struct pt_regs *regs)
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* If VMX is in use, the VRs now hold checkpointed values,
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* so we don't want to load the VRs from the thread_struct.
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*/
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tm_recheckpoint(¤t->thread, orig_msr | MSR_FP);
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tm_recheckpoint(¤t->thread);
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/* If VMX is in use, get the transactional values back */
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if (orig_msr & MSR_VEC) {
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regs->nip, regs->msr);
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tm_reclaim_current(TM_CAUSE_FAC_UNAV);
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current->thread.load_vec = 1;
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tm_recheckpoint(¤t->thread, orig_msr | MSR_VEC);
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tm_recheckpoint(¤t->thread);
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current->thread.used_vr = 1;
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if (orig_msr & MSR_FP) {
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void vsx_unavailable_tm(struct pt_regs *regs)
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{
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unsigned long orig_msr = regs->msr;
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/* See the comments in fp_unavailable_tm(). This works similarly,
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* though we're loading both FP and VEC registers in here.
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*
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current->thread.used_vsr = 1;
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/* If FP and VMX are already loaded, we have all the state we need */
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if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
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regs->msr |= MSR_VSX;
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return;
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}
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/* This reclaims FP and/or VR regs if they're already enabled */
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tm_reclaim_current(TM_CAUSE_FAC_UNAV);
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current->thread.load_vec = 1;
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current->thread.load_fp = 1;
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/* This loads & recheckpoints FP and VRs; but we have
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* to be sure not to overwrite previously-valid state.
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*/
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tm_recheckpoint(¤t->thread, orig_msr | MSR_FP | MSR_VEC);
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tm_recheckpoint(¤t->thread);
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msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC));
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if (orig_msr & MSR_FP)
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load_fp_state(¤t->thread.fp_state);
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if (orig_msr & MSR_VEC)
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load_vr_state(¤t->thread.vr_state);
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msr_check_and_set(MSR_FP | MSR_VEC);
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load_fp_state(¤t->thread.fp_state);
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load_vr_state(¤t->thread.vr_state);
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}
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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