clk: prima2: enable dt-binding clkdev mapping
this patche deletes hard code that registers clkdev by things like: clk_register_clkdev(clk, NULL, "b0030000.nand"); clk_register_clkdev(clk, NULL, "b0040000.audio"); clk_register_clkdev(clk, NULL, "b0080000.usp"); prima2 clock controller becomes a clock provider and every dt node just declares its clock sources by dt prop. it also makes us easier to extend this driver to support both prima2 and marco as marco has different address mapping with prima2. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>hifive-unleashed-5.1
Barry Song
Mike Turquette
parent
38a8b096f8
commit
eb8b8f2e71
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@ -0,0 +1,73 @@
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* Clock bindings for CSR SiRFprimaII
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Required properties:
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- compatible: Should be "sirf,prima2-clkc"
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- reg: Address and length of the register set
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- interrupts: Should contain clock controller interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of prima2
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clocks and IDs.
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Clock ID
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---------------------------
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rtc 0
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osc 1
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pll1 2
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pll2 3
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pll3 4
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mem 5
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sys 6
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security 7
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dsp 8
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gps 9
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mf 10
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io 11
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cpu 12
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uart0 13
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uart1 14
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uart2 15
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tsc 16
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i2c0 17
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i2c1 18
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spi0 19
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spi1 20
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pwmc 21
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efuse 22
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pulse 23
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dmac0 24
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dmac1 25
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nand 26
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audio 27
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usp0 28
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usp1 29
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usp2 30
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vip 31
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gfx 32
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mm 33
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lcd 34
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vpp 35
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mmc01 36
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mmc23 37
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mmc45 38
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usbpll 39
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usb0 40
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usb1 41
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Examples:
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clks: clock-controller@88000000 {
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compatible = "sirf,prima2-clkc";
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reg = <0x88000000 0x1000>;
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interrupts = <3>;
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#clock-cells = <1>;
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};
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i2c0: i2c@b00e0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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clocks = <&clks 17>;
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};
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@ -58,10 +58,11 @@
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#size-cells = <1>;
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ranges = <0x88000000 0x88000000 0x40000>;
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clock-controller@88000000 {
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clks: clock-controller@88000000 {
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compatible = "sirf,prima2-clkc";
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reg = <0x88000000 0x1000>;
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interrupts = <3>;
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#clock-cells = <1>;
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};
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reset-controller@88010000 {
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@ -85,6 +86,7 @@
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compatible = "sirf,prima2-memc";
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reg = <0x90000000 0x10000>;
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interrupts = <27>;
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clocks = <&clks 5>;
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};
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};
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@ -104,6 +106,7 @@
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compatible = "sirf,prima2-vpp";
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reg = <0x90020000 0x10000>;
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interrupts = <31>;
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clocks = <&clks 35>;
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};
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};
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@ -117,6 +120,7 @@
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compatible = "powervr,sgx531";
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reg = <0x98000000 0x8000000>;
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interrupts = <6>;
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clocks = <&clks 32>;
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};
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};
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@ -130,6 +134,7 @@
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compatible = "sirf,prima2-video-codec";
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reg = <0xa0000000 0x8000000>;
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interrupts = <5>;
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clocks = <&clks 33>;
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};
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};
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@ -149,12 +154,14 @@
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compatible = "sirf,prima2-gps";
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reg = <0xa8010000 0x10000>;
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interrupts = <7>;
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clocks = <&clks 9>;
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};
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dsp@a9000000 {
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compatible = "sirf,prima2-dsp";
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reg = <0xa9000000 0x1000000>;
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interrupts = <8>;
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clocks = <&clks 8>;
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};
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};
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@ -174,12 +181,14 @@
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compatible = "sirf,prima2-nand";
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reg = <0xb0030000 0x10000>;
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interrupts = <41>;
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clocks = <&clks 26>;
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};
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audio@b0040000 {
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compatible = "sirf,prima2-audio";
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reg = <0xb0040000 0x10000>;
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interrupts = <35>;
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clocks = <&clks 27>;
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};
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uart0: uart@b0050000 {
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@ -187,6 +196,7 @@
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compatible = "sirf,prima2-uart";
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reg = <0xb0050000 0x10000>;
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interrupts = <17>;
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clocks = <&clks 13>;
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};
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uart1: uart@b0060000 {
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@ -194,6 +204,7 @@
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compatible = "sirf,prima2-uart";
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reg = <0xb0060000 0x10000>;
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interrupts = <18>;
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clocks = <&clks 14>;
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};
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uart2: uart@b0070000 {
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@ -201,6 +212,7 @@
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compatible = "sirf,prima2-uart";
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reg = <0xb0070000 0x10000>;
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interrupts = <19>;
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clocks = <&clks 15>;
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};
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usp0: usp@b0080000 {
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@ -208,6 +220,7 @@
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compatible = "sirf,prima2-usp";
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reg = <0xb0080000 0x10000>;
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interrupts = <20>;
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clocks = <&clks 28>;
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};
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usp1: usp@b0090000 {
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@ -215,6 +228,7 @@
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compatible = "sirf,prima2-usp";
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reg = <0xb0090000 0x10000>;
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interrupts = <21>;
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clocks = <&clks 29>;
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};
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usp2: usp@b00a0000 {
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@ -222,6 +236,7 @@
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compatible = "sirf,prima2-usp";
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reg = <0xb00a0000 0x10000>;
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interrupts = <22>;
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clocks = <&clks 30>;
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};
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dmac0: dma-controller@b00b0000 {
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@ -229,6 +244,7 @@
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compatible = "sirf,prima2-dmac";
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reg = <0xb00b0000 0x10000>;
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interrupts = <12>;
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clocks = <&clks 24>;
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};
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dmac1: dma-controller@b0160000 {
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@ -236,11 +252,13 @@
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compatible = "sirf,prima2-dmac";
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reg = <0xb0160000 0x10000>;
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interrupts = <13>;
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clocks = <&clks 25>;
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};
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vip@b00C0000 {
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compatible = "sirf,prima2-vip";
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reg = <0xb00C0000 0x10000>;
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clocks = <&clks 31>;
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};
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spi0: spi@b00d0000 {
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@ -248,6 +266,7 @@
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compatible = "sirf,prima2-spi";
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reg = <0xb00d0000 0x10000>;
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interrupts = <15>;
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clocks = <&clks 19>;
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};
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spi1: spi@b0170000 {
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@ -255,6 +274,7 @@
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compatible = "sirf,prima2-spi";
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reg = <0xb0170000 0x10000>;
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interrupts = <16>;
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clocks = <&clks 20>;
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};
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i2c0: i2c@b00e0000 {
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@ -262,6 +282,7 @@
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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clocks = <&clks 17>;
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};
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i2c1: i2c@b00f0000 {
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@ -269,12 +290,14 @@
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compatible = "sirf,prima2-i2c";
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reg = <0xb00f0000 0x10000>;
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interrupts = <25>;
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clocks = <&clks 18>;
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};
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tsc@b0110000 {
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compatible = "sirf,prima2-tsc";
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reg = <0xb0110000 0x10000>;
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interrupts = <33>;
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clocks = <&clks 16>;
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};
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gpio: pinctrl@b0120000 {
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@ -507,17 +530,20 @@
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pwm@b0130000 {
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compatible = "sirf,prima2-pwm";
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reg = <0xb0130000 0x10000>;
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clocks = <&clks 21>;
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};
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efusesys@b0140000 {
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compatible = "sirf,prima2-efuse";
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reg = <0xb0140000 0x10000>;
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clocks = <&clks 22>;
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};
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pulsec@b0150000 {
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compatible = "sirf,prima2-pulsec";
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reg = <0xb0150000 0x10000>;
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interrupts = <48>;
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clocks = <&clks 23>;
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};
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pci-iobg {
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@ -616,12 +642,14 @@
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compatible = "chipidea,ci13611a-prima2";
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reg = <0xb8000000 0x10000>;
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interrupts = <10>;
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clocks = <&clks 40>;
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};
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usb1: usb@b00f0000 {
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compatible = "chipidea,ci13611a-prima2";
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reg = <0xb8010000 0x10000>;
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interrupts = <11>;
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clocks = <&clks 41>;
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};
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sata@b00f0000 {
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@ -634,6 +662,7 @@
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compatible = "sirf,prima2-security";
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reg = <0xb8030000 0x10000>;
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interrupts = <42>;
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clocks = <&clks 7>;
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};
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};
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};
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@ -1025,20 +1025,67 @@ static struct of_device_id rsc_ids[] = {
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{},
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};
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enum prima2_clk_index {
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/* 0 1 2 3 4 5 6 7 8 9 */
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rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
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mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
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spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
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usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
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usb0, usb1, maxclk,
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};
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static __initdata struct clk_hw* prima2_clk_hw_array[maxclk] = {
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NULL, /* dummy */
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NULL,
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&clk_pll1.hw,
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&clk_pll2.hw,
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&clk_pll3.hw,
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&clk_mem.hw,
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&clk_sys.hw,
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&clk_security.hw,
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&clk_dsp.hw,
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&clk_gps.hw,
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&clk_mf.hw,
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&clk_io.hw,
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&clk_cpu.hw,
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&clk_uart0.hw,
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&clk_uart1.hw,
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&clk_uart2.hw,
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&clk_tsc.hw,
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&clk_i2c0.hw,
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&clk_i2c1.hw,
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&clk_spi0.hw,
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&clk_spi1.hw,
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&clk_pwmc.hw,
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&clk_efuse.hw,
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&clk_pulse.hw,
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&clk_dmac0.hw,
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&clk_dmac1.hw,
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&clk_nand.hw,
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&clk_audio.hw,
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&clk_usp0.hw,
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&clk_usp1.hw,
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&clk_usp2.hw,
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&clk_vip.hw,
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&clk_gfx.hw,
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&clk_mm.hw,
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&clk_lcd.hw,
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&clk_vpp.hw,
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&clk_mmc01.hw,
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&clk_mmc23.hw,
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&clk_mmc45.hw,
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&usb_pll_clk_hw,
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&clk_usb0.hw,
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&clk_usb1.hw,
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};
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static struct clk *prima2_clks[maxclk];
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static struct clk_onecell_data clk_data;
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void __init sirfsoc_of_clk_init(void)
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{
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struct clk *clk;
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struct device_node *np;
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np = of_find_matching_node(NULL, clkc_ids);
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if (!np)
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panic("unable to find compatible clkc node in dtb\n");
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sirfsoc_clk_vbase = of_iomap(np, 0);
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if (!sirfsoc_clk_vbase)
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panic("unable to map clkc registers\n");
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of_node_put(np);
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int i;
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np = of_find_matching_node(NULL, rsc_ids);
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if (!np)
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@ -1050,122 +1097,30 @@ void __init sirfsoc_of_clk_init(void)
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of_node_put(np);
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np = of_find_matching_node(NULL, clkc_ids);
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if (!np)
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return;
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sirfsoc_clk_vbase = of_iomap(np, 0);
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if (!sirfsoc_clk_vbase)
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panic("unable to map clkc registers\n");
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/* These are always available (RTC and 26MHz OSC)*/
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clk = clk_register_fixed_rate(NULL, "rtc", NULL,
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prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
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CLK_IS_ROOT, 32768);
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BUG_ON(IS_ERR(clk));
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clk = clk_register_fixed_rate(NULL, "osc", NULL,
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prima2_clks[osc]= clk_register_fixed_rate(NULL, "osc", NULL,
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CLK_IS_ROOT, 26000000);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_pll1.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_pll2.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_pll3.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_mem.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_sys.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_security.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b8030000.security");
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clk = clk_register(NULL, &clk_dsp.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_gps.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "a8010000.gps");
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clk = clk_register(NULL, &clk_mf.hw);
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BUG_ON(IS_ERR(clk));
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clk = clk_register(NULL, &clk_io.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "io");
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clk = clk_register(NULL, &clk_cpu.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "cpu");
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clk = clk_register(NULL, &clk_uart0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0050000.uart");
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clk = clk_register(NULL, &clk_uart1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0060000.uart");
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clk = clk_register(NULL, &clk_uart2.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0070000.uart");
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clk = clk_register(NULL, &clk_tsc.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0110000.tsc");
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clk = clk_register(NULL, &clk_i2c0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00e0000.i2c");
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clk = clk_register(NULL, &clk_i2c1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00f0000.i2c");
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clk = clk_register(NULL, &clk_spi0.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b00d0000.spi");
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clk = clk_register(NULL, &clk_spi1.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0170000.spi");
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clk = clk_register(NULL, &clk_pwmc.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0130000.pwm");
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clk = clk_register(NULL, &clk_efuse.hw);
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BUG_ON(IS_ERR(clk));
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clk_register_clkdev(clk, NULL, "b0140000.efusesys");
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clk = clk_register(NULL, &clk_pulse.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b0150000.pulsec");
|
||||
clk = clk_register(NULL, &clk_dmac0.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
|
||||
clk = clk_register(NULL, &clk_dmac1.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
|
||||
clk = clk_register(NULL, &clk_nand.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b0030000.nand");
|
||||
clk = clk_register(NULL, &clk_audio.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b0040000.audio");
|
||||
clk = clk_register(NULL, &clk_usp0.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b0080000.usp");
|
||||
clk = clk_register(NULL, &clk_usp1.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b0090000.usp");
|
||||
clk = clk_register(NULL, &clk_usp2.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b00a0000.usp");
|
||||
clk = clk_register(NULL, &clk_vip.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b00c0000.vip");
|
||||
clk = clk_register(NULL, &clk_gfx.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "98000000.graphics");
|
||||
clk = clk_register(NULL, &clk_mm.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "a0000000.multimedia");
|
||||
clk = clk_register(NULL, &clk_lcd.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "90010000.display");
|
||||
clk = clk_register(NULL, &clk_vpp.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "90020000.vpp");
|
||||
clk = clk_register(NULL, &clk_mmc01.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk = clk_register(NULL, &clk_mmc23.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk = clk_register(NULL, &clk_mmc45.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk = clk_register(NULL, &usb_pll_clk_hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk = clk_register(NULL, &clk_usb0.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b00e0000.usb");
|
||||
clk = clk_register(NULL, &clk_usb1.hw);
|
||||
BUG_ON(IS_ERR(clk));
|
||||
clk_register_clkdev(clk, NULL, "b00f0000.usb");
|
||||
for (i = pll1; i < maxclk; i++) {
|
||||
prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
|
||||
BUG_ON(!prima2_clks[i]);
|
||||
}
|
||||
clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
|
||||
clk_register_clkdev(prima2_clks[io], NULL, "io");
|
||||
clk_register_clkdev(prima2_clks[mem], NULL, "mem");
|
||||
|
||||
clk_data.clks = prima2_clks;
|
||||
clk_data.clk_num = maxclk;
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue