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ASoC: rockchip: i2s: separate capture and playback

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If we only clear the tx/rx state when both are disabled it is not
possible to start/stop one multiple times while the other is running.
Since the two are independently controlled, treat them as such and
remove the false dependency between capture and playback.

Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
John Keeping 2015-12-09 10:32:26 +00:00 committed by Mark Brown
parent 7fd9093a75
commit eba65d179c
1 changed files with 32 additions and 40 deletions
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72
sound/soc/rockchip/rockchip_i2s.c
View file

@ -82,8 +82,8 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
regmap_update_bits(i2s->regmap, I2S_XFER, regmap_update_bits(i2s->regmap, I2S_XFER,
I2S_XFER_TXS_START | I2S_XFER_RXS_START, I2S_XFER_TXS_START,
I2S_XFER_TXS_START | I2S_XFER_RXS_START); I2S_XFER_TXS_START);
i2s->tx_start = true; i2s->tx_start = true;
} else { } else {
@ -92,27 +92,23 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
regmap_update_bits(i2s->regmap, I2S_DMACR, regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
if (!i2s->rx_start) { regmap_update_bits(i2s->regmap, I2S_XFER,
regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START,
I2S_XFER_TXS_START | I2S_XFER_TXS_STOP);
I2S_XFER_RXS_START,
I2S_XFER_TXS_STOP |
I2S_XFER_RXS_STOP);
regmap_update_bits(i2s->regmap, I2S_CLR, regmap_update_bits(i2s->regmap, I2S_CLR,
I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC,
I2S_CLR_TXC | I2S_CLR_RXC); I2S_CLR_TXC);
regmap_read(i2s->regmap, I2S_CLR, &val);
/* Should wait for clear operation to finish */
while (val & I2S_CLR_TXC) {
regmap_read(i2s->regmap, I2S_CLR, &val); regmap_read(i2s->regmap, I2S_CLR, &val);
retry--;
/* Should wait for clear operation to finish */ if (!retry) {
while (val) { dev_warn(i2s->dev, "fail to clear\n");
regmap_read(i2s->regmap, I2S_CLR, &val); break;
retry--;
if (!retry) {
dev_warn(i2s->dev, "fail to clear\n");
break;
}
} }
} }
} }
@ -128,8 +124,8 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
regmap_update_bits(i2s->regmap, I2S_XFER, regmap_update_bits(i2s->regmap, I2S_XFER,
I2S_XFER_TXS_START | I2S_XFER_RXS_START, I2S_XFER_RXS_START,
I2S_XFER_TXS_START | I2S_XFER_RXS_START); I2S_XFER_RXS_START);
i2s->rx_start = true; i2s->rx_start = true;
} else { } else {
@ -138,27 +134,23 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
regmap_update_bits(i2s->regmap, I2S_DMACR, regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
if (!i2s->tx_start) { regmap_update_bits(i2s->regmap, I2S_XFER,
regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_RXS_START,
I2S_XFER_TXS_START | I2S_XFER_RXS_STOP);
I2S_XFER_RXS_START,
I2S_XFER_TXS_STOP |
I2S_XFER_RXS_STOP);
regmap_update_bits(i2s->regmap, I2S_CLR, regmap_update_bits(i2s->regmap, I2S_CLR,
I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_RXC,
I2S_CLR_TXC | I2S_CLR_RXC); I2S_CLR_RXC);
regmap_read(i2s->regmap, I2S_CLR, &val);
/* Should wait for clear operation to finish */
while (val & I2S_CLR_RXC) {
regmap_read(i2s->regmap, I2S_CLR, &val); regmap_read(i2s->regmap, I2S_CLR, &val);
retry--;
/* Should wait for clear operation to finish */ if (!retry) {
while (val) { dev_warn(i2s->dev, "fail to clear\n");
regmap_read(i2s->regmap, I2S_CLR, &val); break;
retry--;
if (!retry) {
dev_warn(i2s->dev, "fail to clear\n");
break;
}
} }
} }
} }