Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Increase cp0 compare clockevent min_delta_ns from 0x30 to 0x300. [MIPS] Cache: Provide more information on cache policy on bootup. [MIPS] Fix aliasing bug in copy_user_highpage, take 2. [MIPS] VPE loader: convert from struct class_ device to struct device [MIPS] MIPSsim: Fix booting from NFS root [MIPS] Alchemy: Get rid of au1xxx_irq_map_t. [MIPS] Alchemy: Get rid of au_ffz(). [MIPS] Alchemy: Get rid of au_ffs(). [MIPS] Alchemy: cleanup interrupt code. [MIPS] Lasat: Fix build by conversion to irq_cpu.c. [MIPS] Lasat: Add #ifndef ... #endif include warpper to lasatint.h. [MIPS] IP22: Enable -Werror. [MIPS] IP22: Fix warning. [MIPS] IP22: Complain if requesting the front panel irq failed. [MIPS] vmlinux.lds.S: Handle KPROBES_TEXT. [MIPS] vmlinux.lds.S: Fix handling of .notes in final link. [MIPS] vmlinux.lds.S: Remove duplicate comment. [MIPS] MSP71XX: Add workarounds file. [MIPS] IP32: Fix build by conversion to irq_cpu.c.hifive-unleashed-5.1
Linus Torvalds
commit
ebc283118e
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@ -133,6 +133,7 @@ config LASAT
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select DMA_NONCOHERENT
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select SYS_HAS_EARLY_PRINTK
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select HW_HAS_PCI
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select IRQ_CPU
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select PCI_GT64XXX_PCI0
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select MIPS_NILE4
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select R5000_CPU_SCACHE
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@ -410,6 +411,7 @@ config SGI_IP32
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select BOOT_ELF32
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select IRQ_CPU
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select R5000_CPU_SCACHE
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select RM7000_CPU_SCACHE
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select SYS_HAS_CPU_R5000
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@ -54,7 +54,7 @@
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* Careful if you change match 2 request!
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* The interrupt handler is called directly from the low level dispatch code.
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*/
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au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
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#if defined(CONFIG_SOC_AU1000)
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{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
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@ -859,7 +859,7 @@ dbdma_interrupt(int irq, void *dev_id)
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intstat = dbdma_gptr->ddma_intstat;
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au_sync();
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chan_index = au_ffs(intstat) - 1;
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chan_index = ffs(intstat);
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ctp = chan_tab_ptr[chan_index];
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cp = ctp->chan_ptr;
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File diff suppressed because it is too large
Load Diff
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@ -79,7 +79,7 @@ char irq_tab_alchemy[][5] __initdata = {
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#endif
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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#ifndef CONFIG_MIPS_MIRAGE
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#ifdef CONFIG_MIPS_DB1550
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@ -58,7 +58,7 @@ char irq_tab_alchemy[][5] __initdata = {
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[7] = { -1, INTD, INTC, INTX, INTX}, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
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};
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
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{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
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{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
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@ -47,7 +47,7 @@
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#include <asm/system.h>
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#include <asm/mach-au1x00/au1000.h>
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
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};
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@ -47,7 +47,7 @@
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#include <asm/system.h>
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#include <asm/mach-au1x00/au1000.h>
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
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{ AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
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{ AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#
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@ -54,7 +54,7 @@
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#define PB1200_INT_END DB1200_INT_END
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#endif
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
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};
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@ -74,7 +74,7 @@ irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
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bcsr->int_status = bisr;
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for( ; bisr; bisr &= (bisr-1) )
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{
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extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
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extirq_nr = PB1200_INT_BEGIN + au_ffs(bisr);
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/* Ack and dispatch IRQ */
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do_IRQ(extirq_nr);
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}
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@ -52,7 +52,7 @@ char irq_tab_alchemy[][5] __initdata = {
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[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot */
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};
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
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{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
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{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
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@ -52,7 +52,7 @@ char irq_tab_alchemy[][5] __initdata = {
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[13] = { -1, INTA, INTB, INTC, INTD}, /* IDSEL 13 - PCI slot 1 (right) */
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};
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
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};
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@ -47,7 +47,7 @@
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#include <asm/system.h>
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#include <asm/au1000.h>
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au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
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struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
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{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
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{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
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{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
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@ -421,7 +421,7 @@ void __cpuinit mips_clockevent_init(void)
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cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
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cd->shift = 32;
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x30, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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@ -104,7 +104,7 @@ static int __init set_raw_show_trace(char *str)
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__setup("raw_show_trace", set_raw_show_trace);
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#endif
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static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
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static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
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{
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unsigned long sp = regs->regs[29];
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unsigned long ra = regs->regs[31];
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@ -126,7 +126,8 @@ static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
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* This routine abuses get_user()/put_user() to reference pointers
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* with at least a bit of error checking ...
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*/
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static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
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static void show_stacktrace(struct task_struct *task,
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const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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long stackdata;
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@ -203,7 +204,7 @@ static void show_code(unsigned int __user *pc)
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}
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}
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void show_regs(struct pt_regs *regs)
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static void __show_regs(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int cause = regs->cp0_cause;
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@ -299,9 +300,17 @@ void show_regs(struct pt_regs *regs)
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cpu_name_string());
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}
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void show_registers(struct pt_regs *regs)
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/*
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* FIXME: really the generic show_regs should take a const pointer argument.
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*/
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void show_regs(struct pt_regs *regs)
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{
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show_regs(regs);
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__show_regs((struct pt_regs *)regs);
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}
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void show_registers(const struct pt_regs *regs)
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{
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__show_regs(regs);
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print_modules();
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printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
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current->comm, current->pid, current_thread_info(), current);
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@ -312,7 +321,7 @@ void show_registers(struct pt_regs *regs)
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static DEFINE_SPINLOCK(die_lock);
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void __noreturn die(const char * str, struct pt_regs * regs)
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void __noreturn die(const char * str, const struct pt_regs * regs)
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{
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static int die_counter;
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#ifdef CONFIG_MIPS_MT_SMTC
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@ -5,6 +5,10 @@
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#define mips mips
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OUTPUT_ARCH(mips)
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ENTRY(kernel_entry)
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PHDRS {
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text PT_LOAD FLAGS(7); /* RWX */
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note PT_NOTE FLAGS(4); /* R__ */
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}
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jiffies = JIFFIES;
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SECTIONS
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@ -21,7 +25,6 @@ SECTIONS
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* >= 0xa800 0000 0030 0000 otherwise
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*/
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/* . = 0xa800000000300000; */
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/* . = 0xa800000000300000; */
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. = 0xffffffff80300000;
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#endif
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@ -32,9 +35,10 @@ SECTIONS
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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*(.fixup)
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*(.gnu.warning)
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} =0
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} :text = 0
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_etext = .; /* End of text section */
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/* Exception table */
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@ -51,6 +55,10 @@ SECTIONS
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*(__dbe_table)
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__stop___dbe_table = .;
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}
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NOTES :text :note
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.dummy : { *(.dummy) } :text
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RODATA
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/* writeable */
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@ -201,7 +209,4 @@ SECTIONS
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*(.gptab.bss)
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*(.gptab.sbss)
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}
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.note : {
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*(.note)
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}
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}
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@ -1317,7 +1317,8 @@ static void kspd_sp_exit( int sp_id)
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}
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#endif
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static ssize_t store_kill(struct class_device *dev, const char *buf, size_t len)
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static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t len)
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{
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struct vpe *vpe = get_vpe(tclimit);
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struct vpe_notifications *not;
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@ -1334,14 +1335,16 @@ static ssize_t store_kill(struct class_device *dev, const char *buf, size_t len)
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return len;
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}
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static ssize_t show_ntcs(struct class_device *cd, char *buf)
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static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr,
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char *buf)
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{
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struct vpe *vpe = get_vpe(tclimit);
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return sprintf(buf, "%d\n", vpe->ntcs);
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}
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static ssize_t store_ntcs(struct class_device *dev, const char *buf, size_t len)
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static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t len)
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{
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struct vpe *vpe = get_vpe(tclimit);
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unsigned long new;
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@ -1362,13 +1365,13 @@ out_einval:
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return -EINVAL;;
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}
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static struct class_device_attribute vpe_class_attributes[] = {
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static struct device_attribute vpe_class_attributes[] = {
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__ATTR(kill, S_IWUSR, NULL, store_kill),
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__ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs),
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{}
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};
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static void vpe_class_device_release(struct class_device *cd)
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static void vpe_device_release(struct device *cd)
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{
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kfree(cd);
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}
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@ -1376,11 +1379,11 @@ static void vpe_class_device_release(struct class_device *cd)
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struct class vpe_class = {
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.name = "vpe",
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.owner = THIS_MODULE,
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.release = vpe_class_device_release,
|
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.class_dev_attrs = vpe_class_attributes,
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.dev_release = vpe_device_release,
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.dev_attrs = vpe_class_attributes,
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};
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|
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struct class_device vpe_device;
|
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struct device vpe_device;
|
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|
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static int __init vpe_module_init(void)
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{
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|
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@ -1423,12 +1426,12 @@ static int __init vpe_module_init(void)
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goto out_chrdev;
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}
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|
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class_device_initialize(&vpe_device);
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device_initialize(&vpe_device);
|
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vpe_device.class = &vpe_class,
|
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vpe_device.parent = NULL,
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strlcpy(vpe_device.class_id, "vpe1", BUS_ID_SIZE);
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strlcpy(vpe_device.bus_id, "vpe1", BUS_ID_SIZE);
|
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vpe_device.devt = MKDEV(major, minor);
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err = class_device_add(&vpe_device);
|
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err = device_add(&vpe_device);
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if (err) {
|
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printk(KERN_ERR "Adding vpe_device failed\n");
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goto out_class;
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|
|
@ -1573,7 +1576,7 @@ static void __exit vpe_module_exit(void)
|
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}
|
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}
|
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|
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class_device_del(&vpe_device);
|
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device_del(&vpe_device);
|
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unregister_chrdev(major, module_name);
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}
|
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|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
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#include <linux/kernel_stat.h>
|
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|
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#include <asm/bootinfo.h>
|
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#include <asm/irq_cpu.h>
|
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#include <asm/lasat/lasatint.h>
|
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#include <asm/time.h>
|
||||
#include <asm/gdb-stub.h>
|
||||
|
|
@ -88,7 +89,7 @@ asmlinkage void plat_irq_dispatch(void)
|
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int irq;
|
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|
||||
if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
|
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ll_timer_interrupt(7);
|
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do_IRQ(7);
|
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return;
|
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}
|
||||
|
||||
|
|
@ -96,7 +97,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
|
||||
/* if int_status == 0, then the interrupt has already been cleared */
|
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if (int_status) {
|
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irq = ls1bit32(int_status);
|
||||
irq = LASATINT_BASE + ls1bit32(int_status);
|
||||
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
|
@ -125,6 +126,7 @@ void __init arch_init_irq(void)
|
|||
panic("arch_init_irq: mips_machtype incorrect");
|
||||
}
|
||||
|
||||
for (i = 0; i <= LASATINT_END; i++)
|
||||
mips_cpu_irq_init();
|
||||
for (i = LASATINT_BASE; i <= LASATINT_END; i++)
|
||||
set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,8 +28,5 @@ char * __init prom_getcmdline(void)
|
|||
|
||||
void __init prom_init_cmdline(void)
|
||||
{
|
||||
char *cp;
|
||||
cp = arcs_cmdline;
|
||||
/* Get boot line from environment? */
|
||||
*cp = '\0';
|
||||
/* XXX: Get boot line from environment? */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -983,11 +983,15 @@ static void __init probe_pcache(void)
|
|||
|
||||
printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
|
||||
icache_size >> 10,
|
||||
cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
|
||||
cpu_has_vtag_icache ? "VIVT" : "VIPT",
|
||||
way_string[c->icache.ways], c->icache.linesz);
|
||||
|
||||
printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
|
||||
dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
|
||||
printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
|
||||
dcache_size >> 10, way_string[c->dcache.ways],
|
||||
(c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
|
||||
(c->dcache.flags & MIPS_CACHE_ALIASES) ?
|
||||
"cache aliases" : "no aliases",
|
||||
c->dcache.linesz);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -211,7 +211,7 @@ void copy_user_highpage(struct page *to, struct page *from,
|
|||
void *vfrom, *vto;
|
||||
|
||||
vto = kmap_atomic(to, KM_USER1);
|
||||
if (cpu_has_dc_aliases && !Page_dcache_dirty(from)) {
|
||||
if (cpu_has_dc_aliases && page_mapped(from)) {
|
||||
vfrom = kmap_coherent(from, vaddr);
|
||||
copy_page(vto, vfrom);
|
||||
kunmap_coherent();
|
||||
|
|
@ -234,12 +234,15 @@ void copy_to_user_page(struct vm_area_struct *vma,
|
|||
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||
unsigned long len)
|
||||
{
|
||||
if (cpu_has_dc_aliases) {
|
||||
if (cpu_has_dc_aliases && page_mapped(page)) {
|
||||
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||
memcpy(vto, src, len);
|
||||
kunmap_coherent();
|
||||
} else
|
||||
} else {
|
||||
memcpy(dst, src, len);
|
||||
if (cpu_has_dc_aliases)
|
||||
SetPageDcacheDirty(page);
|
||||
}
|
||||
if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
|
||||
flush_cache_page(vma, vaddr, page_to_pfn(page));
|
||||
}
|
||||
|
|
@ -250,13 +253,15 @@ void copy_from_user_page(struct vm_area_struct *vma,
|
|||
struct page *page, unsigned long vaddr, void *dst, const void *src,
|
||||
unsigned long len)
|
||||
{
|
||||
if (cpu_has_dc_aliases) {
|
||||
void *vfrom =
|
||||
kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||
if (cpu_has_dc_aliases && page_mapped(page)) {
|
||||
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
|
||||
memcpy(dst, vfrom, len);
|
||||
kunmap_coherent();
|
||||
} else
|
||||
} else {
|
||||
memcpy(dst, src, len);
|
||||
if (cpu_has_dc_aliases)
|
||||
SetPageDcacheDirty(page);
|
||||
}
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(copy_from_user_page);
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/pci.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/lasat/lasatint.h>
|
||||
|
||||
extern struct pci_ops nile4_pci_ops;
|
||||
extern struct pci_ops gt64xxx_pci0_ops;
|
||||
|
|
@ -54,15 +55,15 @@ static int __init lasat_pci_setup(void)
|
|||
|
||||
arch_initcall(lasat_pci_setup);
|
||||
|
||||
#define LASATINT_ETH1 0
|
||||
#define LASATINT_ETH0 1
|
||||
#define LASATINT_HDC 2
|
||||
#define LASATINT_COMP 3
|
||||
#define LASATINT_HDLC 4
|
||||
#define LASATINT_PCIA 5
|
||||
#define LASATINT_PCIB 6
|
||||
#define LASATINT_PCIC 7
|
||||
#define LASATINT_PCID 8
|
||||
#define LASATINT_ETH1 (LASATINT_BASE + 0)
|
||||
#define LASATINT_ETH0 (LASATINT_BASE + 1)
|
||||
#define LASATINT_HDC (LASATINT_BASE + 2)
|
||||
#define LASATINT_COMP (LASATINT_BASE + 3)
|
||||
#define LASATINT_HDLC (LASATINT_BASE + 4)
|
||||
#define LASATINT_PCIA (LASATINT_BASE + 5)
|
||||
#define LASATINT_PCIB (LASATINT_BASE + 6)
|
||||
#define LASATINT_PCIC (LASATINT_BASE + 7)
|
||||
#define LASATINT_PCID (LASATINT_BASE + 8)
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -7,3 +7,5 @@ obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-berr.o \
|
|||
ip22-time.o ip22-nvram.o ip22-platform.o ip22-reset.o ip22-setup.o
|
||||
|
||||
obj-$(CONFIG_EISA) += ip22-eisa.o
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
|
|
|
|||
|
|
@ -232,11 +232,18 @@ static struct notifier_block panic_block = {
|
|||
|
||||
static int __init reboot_setup(void)
|
||||
{
|
||||
int res;
|
||||
|
||||
_machine_restart = sgi_machine_restart;
|
||||
_machine_halt = sgi_machine_halt;
|
||||
pm_power_off = sgi_machine_power_off;
|
||||
|
||||
request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL);
|
||||
res = request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL);
|
||||
if (res) {
|
||||
printk(KERN_ERR "Allocation of front panel IRQ failed\n");
|
||||
return res;
|
||||
}
|
||||
|
||||
init_timer(&blink_timer);
|
||||
blink_timer.function = blink_timeout;
|
||||
atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/random.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/signal.h>
|
||||
#include <asm/system.h>
|
||||
|
|
@ -46,7 +47,8 @@ static void inline flush_mace_bus(void)
|
|||
#define DBG(x...)
|
||||
#endif
|
||||
|
||||
/* O2 irq map
|
||||
/*
|
||||
* O2 irq map
|
||||
*
|
||||
* IP0 -> software (ignored)
|
||||
* IP1 -> software (ignored)
|
||||
|
|
@ -55,60 +57,60 @@ static void inline flush_mace_bus(void)
|
|||
* IP4 -> (irq2) X unknown
|
||||
* IP5 -> (irq3) X unknown
|
||||
* IP6 -> (irq4) X unknown
|
||||
* IP7 -> (irq5) 0 CPU count/compare timer (system timer)
|
||||
* IP7 -> (irq5) 7 CPU count/compare timer (system timer)
|
||||
*
|
||||
* crime: (C)
|
||||
*
|
||||
* CRIME_INT_STAT 31:0:
|
||||
*
|
||||
* 0 -> 1 Video in 1
|
||||
* 1 -> 2 Video in 2
|
||||
* 2 -> 3 Video out
|
||||
* 3 -> 4 Mace ethernet
|
||||
* 0 -> 8 Video in 1
|
||||
* 1 -> 9 Video in 2
|
||||
* 2 -> 10 Video out
|
||||
* 3 -> 11 Mace ethernet
|
||||
* 4 -> S SuperIO sub-interrupt
|
||||
* 5 -> M Miscellaneous sub-interrupt
|
||||
* 6 -> A Audio sub-interrupt
|
||||
* 7 -> 8 PCI bridge errors
|
||||
* 8 -> 9 PCI SCSI aic7xxx 0
|
||||
* 9 -> 10 PCI SCSI aic7xxx 1
|
||||
* 10 -> 11 PCI slot 0
|
||||
* 11 -> 12 unused (PCI slot 1)
|
||||
* 12 -> 13 unused (PCI slot 2)
|
||||
* 13 -> 14 unused (PCI shared 0)
|
||||
* 14 -> 15 unused (PCI shared 1)
|
||||
* 15 -> 16 unused (PCI shared 2)
|
||||
* 16 -> 17 GBE0 (E)
|
||||
* 17 -> 18 GBE1 (E)
|
||||
* 18 -> 19 GBE2 (E)
|
||||
* 19 -> 20 GBE3 (E)
|
||||
* 20 -> 21 CPU errors
|
||||
* 21 -> 22 Memory errors
|
||||
* 22 -> 23 RE empty edge (E)
|
||||
* 23 -> 24 RE full edge (E)
|
||||
* 24 -> 25 RE idle edge (E)
|
||||
* 25 -> 26 RE empty level
|
||||
* 26 -> 27 RE full level
|
||||
* 27 -> 28 RE idle level
|
||||
* 28 -> 29 unused (software 0) (E)
|
||||
* 29 -> 30 unused (software 1) (E)
|
||||
* 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
|
||||
* 31 -> 32 VICE
|
||||
* 7 -> 15 PCI bridge errors
|
||||
* 8 -> 16 PCI SCSI aic7xxx 0
|
||||
* 9 -> 17 PCI SCSI aic7xxx 1
|
||||
* 10 -> 18 PCI slot 0
|
||||
* 11 -> 19 unused (PCI slot 1)
|
||||
* 12 -> 20 unused (PCI slot 2)
|
||||
* 13 -> 21 unused (PCI shared 0)
|
||||
* 14 -> 22 unused (PCI shared 1)
|
||||
* 15 -> 23 unused (PCI shared 2)
|
||||
* 16 -> 24 GBE0 (E)
|
||||
* 17 -> 25 GBE1 (E)
|
||||
* 18 -> 26 GBE2 (E)
|
||||
* 19 -> 27 GBE3 (E)
|
||||
* 20 -> 28 CPU errors
|
||||
* 21 -> 29 Memory errors
|
||||
* 22 -> 30 RE empty edge (E)
|
||||
* 23 -> 31 RE full edge (E)
|
||||
* 24 -> 32 RE idle edge (E)
|
||||
* 25 -> 33 RE empty level
|
||||
* 26 -> 34 RE full level
|
||||
* 27 -> 35 RE idle level
|
||||
* 28 -> 36 unused (software 0) (E)
|
||||
* 29 -> 37 unused (software 1) (E)
|
||||
* 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
|
||||
* 31 -> 39 VICE
|
||||
*
|
||||
* S, M, A: Use the MACE ISA interrupt register
|
||||
* MACE_ISA_INT_STAT 31:0
|
||||
*
|
||||
* 0-7 -> 33-40 Audio
|
||||
* 8 -> 41 RTC
|
||||
* 9 -> 42 Keyboard
|
||||
* 0-7 -> 40-47 Audio
|
||||
* 8 -> 48 RTC
|
||||
* 9 -> 49 Keyboard
|
||||
* 10 -> X Keyboard polled
|
||||
* 11 -> 44 Mouse
|
||||
* 11 -> 51 Mouse
|
||||
* 12 -> X Mouse polled
|
||||
* 13-15 -> 46-48 Count/compare timers
|
||||
* 16-19 -> 49-52 Parallel (16 E)
|
||||
* 20-25 -> 53-58 Serial 1 (22 E)
|
||||
* 26-31 -> 59-64 Serial 2 (28 E)
|
||||
* 13-15 -> 53-55 Count/compare timers
|
||||
* 16-19 -> 56-59 Parallel (16 E)
|
||||
* 20-25 -> 60-62 Serial 1 (22 E)
|
||||
* 26-31 -> 66-71 Serial 2 (28 E)
|
||||
*
|
||||
* Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
|
||||
* Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
|
||||
* different IRQ map than IRIX uses, but that's OK as Linux irq handling
|
||||
* is quite different anyway.
|
||||
*/
|
||||
|
|
@ -130,36 +132,6 @@ struct irqaction cpuerr_irq = {
|
|||
.name = "CRIME CPU error",
|
||||
};
|
||||
|
||||
/*
|
||||
* For interrupts wired from a single device to the CPU. Only the clock
|
||||
* uses this it seems, which is IRQ 0 and IP7.
|
||||
*/
|
||||
|
||||
static void enable_cpu_irq(unsigned int irq)
|
||||
{
|
||||
set_c0_status(STATUSF_IP7);
|
||||
}
|
||||
|
||||
static void disable_cpu_irq(unsigned int irq)
|
||||
{
|
||||
clear_c0_status(STATUSF_IP7);
|
||||
}
|
||||
|
||||
static void end_cpu_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
|
||||
enable_cpu_irq(irq);
|
||||
}
|
||||
|
||||
static struct irq_chip ip32_cpu_interrupt = {
|
||||
.name = "IP32 CPU",
|
||||
.ack = disable_cpu_irq,
|
||||
.mask = disable_cpu_irq,
|
||||
.mask_ack = disable_cpu_irq,
|
||||
.unmask = enable_cpu_irq,
|
||||
.end = end_cpu_irq,
|
||||
};
|
||||
|
||||
/*
|
||||
* This is for pure CRIME interrupts - ie not MACE. The advantage?
|
||||
* We get to split the register in half and do faster lookups.
|
||||
|
|
@ -422,15 +394,23 @@ static void ip32_irq0(void)
|
|||
uint64_t crime_int;
|
||||
int irq = 0;
|
||||
|
||||
/*
|
||||
* Sanity check interrupt numbering enum.
|
||||
* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
|
||||
* chained.
|
||||
*/
|
||||
BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
|
||||
BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
|
||||
|
||||
crime_int = crime->istat & crime_mask;
|
||||
irq = __ffs(crime_int);
|
||||
irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
|
||||
crime_int = 1 << irq;
|
||||
|
||||
if (crime_int & CRIME_MACEISA_INT_MASK) {
|
||||
unsigned long mace_int = mace->perif.ctrl.istat;
|
||||
irq = __ffs(mace_int & maceisa_mask) + 32;
|
||||
irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
|
||||
}
|
||||
irq++;
|
||||
|
||||
DBG("*irq %u*\n", irq);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
|
@ -457,7 +437,7 @@ static void ip32_irq4(void)
|
|||
|
||||
static void ip32_irq5(void)
|
||||
{
|
||||
do_IRQ(IP32_R4K_TIMER_IRQ);
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
|
|
@ -490,21 +470,25 @@ void __init arch_init_irq(void)
|
|||
mace->perif.ctrl.istat = 0;
|
||||
mace->perif.ctrl.imask = 0;
|
||||
|
||||
for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
|
||||
struct irq_chip *controller;
|
||||
mips_cpu_irq_init();
|
||||
for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
|
||||
struct irq_chip *chip;
|
||||
|
||||
if (irq == IP32_R4K_TIMER_IRQ)
|
||||
controller = &ip32_cpu_interrupt;
|
||||
else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
|
||||
controller = &ip32_mace_interrupt;
|
||||
else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
|
||||
controller = &ip32_macepci_interrupt;
|
||||
else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
|
||||
controller = &ip32_crime_interrupt;
|
||||
else
|
||||
controller = &ip32_maceisa_interrupt;
|
||||
switch (irq) {
|
||||
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
|
||||
chip = &ip32_mace_interrupt;
|
||||
break;
|
||||
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
|
||||
chip = &ip32_macepci_interrupt;
|
||||
break;
|
||||
case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ:
|
||||
chip = &ip32_crime_interrupt;
|
||||
break;
|
||||
default:
|
||||
chip = &ip32_maceisa_interrupt;
|
||||
}
|
||||
|
||||
set_irq_chip(irq, controller);
|
||||
set_irq_chip(irq, chip);
|
||||
}
|
||||
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
|
||||
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ void __init plat_time_init(void)
|
|||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
irq->handler = no_action;
|
||||
setup_irq(IP32_R4K_TIMER_IRQ, irq);
|
||||
setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
|
|
|
|||
|
|
@ -9,86 +9,104 @@
|
|||
#ifndef __ASM_IP32_INTS_H
|
||||
#define __ASM_IP32_INTS_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
/*
|
||||
* This list reflects the assignment of interrupt numbers to
|
||||
* interrupting events. Order is fairly irrelevant to handling
|
||||
* priority. This differs from irix.
|
||||
*/
|
||||
|
||||
/* CPU */
|
||||
#define IP32_R4K_TIMER_IRQ 0
|
||||
enum ip32_irq_no {
|
||||
/*
|
||||
* CPU interrupts are 0 ... 7
|
||||
*/
|
||||
|
||||
/* MACE */
|
||||
#define MACE_VID_IN1_IRQ 1
|
||||
#define MACE_VID_IN2_IRQ 2
|
||||
#define MACE_VID_OUT_IRQ 3
|
||||
#define MACE_ETHERNET_IRQ 4
|
||||
/* SUPERIO, MISC, and AUDIO are MACEISA */
|
||||
#define MACE_PCI_BRIDGE_IRQ 8
|
||||
/*
|
||||
* MACE
|
||||
*/
|
||||
MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8,
|
||||
MACE_VID_IN2_IRQ,
|
||||
MACE_VID_OUT_IRQ,
|
||||
MACE_ETHERNET_IRQ,
|
||||
/* SUPERIO, MISC, and AUDIO are MACEISA */
|
||||
__MACE_SUPERIO,
|
||||
__MACE_MISC,
|
||||
__MACE_AUDIO,
|
||||
MACE_PCI_BRIDGE_IRQ,
|
||||
|
||||
/* MACEPCI */
|
||||
#define MACEPCI_SCSI0_IRQ 9
|
||||
#define MACEPCI_SCSI1_IRQ 10
|
||||
#define MACEPCI_SLOT0_IRQ 11
|
||||
#define MACEPCI_SLOT1_IRQ 12
|
||||
#define MACEPCI_SLOT2_IRQ 13
|
||||
#define MACEPCI_SHARED0_IRQ 14
|
||||
#define MACEPCI_SHARED1_IRQ 15
|
||||
#define MACEPCI_SHARED2_IRQ 16
|
||||
/*
|
||||
* MACEPCI
|
||||
*/
|
||||
MACEPCI_SCSI0_IRQ,
|
||||
MACEPCI_SCSI1_IRQ,
|
||||
MACEPCI_SLOT0_IRQ,
|
||||
MACEPCI_SLOT1_IRQ,
|
||||
MACEPCI_SLOT2_IRQ,
|
||||
MACEPCI_SHARED0_IRQ,
|
||||
MACEPCI_SHARED1_IRQ,
|
||||
MACEPCI_SHARED2_IRQ,
|
||||
|
||||
/* CRIME */
|
||||
#define CRIME_GBE0_IRQ 17
|
||||
#define CRIME_GBE1_IRQ 18
|
||||
#define CRIME_GBE2_IRQ 19
|
||||
#define CRIME_GBE3_IRQ 20
|
||||
#define CRIME_CPUERR_IRQ 21
|
||||
#define CRIME_MEMERR_IRQ 22
|
||||
#define CRIME_RE_EMPTY_E_IRQ 23
|
||||
#define CRIME_RE_FULL_E_IRQ 24
|
||||
#define CRIME_RE_IDLE_E_IRQ 25
|
||||
#define CRIME_RE_EMPTY_L_IRQ 26
|
||||
#define CRIME_RE_FULL_L_IRQ 27
|
||||
#define CRIME_RE_IDLE_L_IRQ 28
|
||||
#define CRIME_SOFT0_IRQ 29
|
||||
#define CRIME_SOFT1_IRQ 30
|
||||
#define CRIME_SOFT2_IRQ 31
|
||||
#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
|
||||
#define CRIME_VICE_IRQ 32
|
||||
/*
|
||||
* CRIME
|
||||
*/
|
||||
CRIME_GBE0_IRQ,
|
||||
CRIME_GBE1_IRQ,
|
||||
CRIME_GBE2_IRQ,
|
||||
CRIME_GBE3_IRQ,
|
||||
CRIME_CPUERR_IRQ,
|
||||
CRIME_MEMERR_IRQ,
|
||||
CRIME_RE_EMPTY_E_IRQ,
|
||||
CRIME_RE_FULL_E_IRQ,
|
||||
CRIME_RE_IDLE_E_IRQ,
|
||||
CRIME_RE_EMPTY_L_IRQ,
|
||||
CRIME_RE_FULL_L_IRQ,
|
||||
CRIME_RE_IDLE_L_IRQ,
|
||||
CRIME_SOFT0_IRQ,
|
||||
CRIME_SOFT1_IRQ,
|
||||
CRIME_SOFT2_IRQ,
|
||||
CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
|
||||
CRIME_VICE_IRQ,
|
||||
|
||||
/* MACEISA */
|
||||
#define MACEISA_AUDIO_SW_IRQ 33
|
||||
#define MACEISA_AUDIO_SC_IRQ 34
|
||||
#define MACEISA_AUDIO1_DMAT_IRQ 35
|
||||
#define MACEISA_AUDIO1_OF_IRQ 36
|
||||
#define MACEISA_AUDIO2_DMAT_IRQ 37
|
||||
#define MACEISA_AUDIO2_MERR_IRQ 38
|
||||
#define MACEISA_AUDIO3_DMAT_IRQ 39
|
||||
#define MACEISA_AUDIO3_MERR_IRQ 40
|
||||
#define MACEISA_RTC_IRQ 41
|
||||
#define MACEISA_KEYB_IRQ 42
|
||||
/* MACEISA_KEYB_POLL is not an IRQ */
|
||||
#define MACEISA_MOUSE_IRQ 44
|
||||
/* MACEISA_MOUSE_POLL is not an IRQ */
|
||||
#define MACEISA_TIMER0_IRQ 46
|
||||
#define MACEISA_TIMER1_IRQ 47
|
||||
#define MACEISA_TIMER2_IRQ 48
|
||||
#define MACEISA_PARALLEL_IRQ 49
|
||||
#define MACEISA_PAR_CTXA_IRQ 50
|
||||
#define MACEISA_PAR_CTXB_IRQ 51
|
||||
#define MACEISA_PAR_MERR_IRQ 52
|
||||
#define MACEISA_SERIAL1_IRQ 53
|
||||
#define MACEISA_SERIAL1_TDMAT_IRQ 54
|
||||
#define MACEISA_SERIAL1_TDMAPR_IRQ 55
|
||||
#define MACEISA_SERIAL1_TDMAME_IRQ 56
|
||||
#define MACEISA_SERIAL1_RDMAT_IRQ 57
|
||||
#define MACEISA_SERIAL1_RDMAOR_IRQ 58
|
||||
#define MACEISA_SERIAL2_IRQ 59
|
||||
#define MACEISA_SERIAL2_TDMAT_IRQ 60
|
||||
#define MACEISA_SERIAL2_TDMAPR_IRQ 61
|
||||
#define MACEISA_SERIAL2_TDMAME_IRQ 62
|
||||
#define MACEISA_SERIAL2_RDMAT_IRQ 63
|
||||
#define MACEISA_SERIAL2_RDMAOR_IRQ 64
|
||||
/*
|
||||
* MACEISA
|
||||
*/
|
||||
MACEISA_AUDIO_SW_IRQ,
|
||||
MACEISA_AUDIO_SC_IRQ,
|
||||
MACEISA_AUDIO1_DMAT_IRQ,
|
||||
MACEISA_AUDIO1_OF_IRQ,
|
||||
MACEISA_AUDIO2_DMAT_IRQ,
|
||||
MACEISA_AUDIO2_MERR_IRQ,
|
||||
MACEISA_AUDIO3_DMAT_IRQ,
|
||||
MACEISA_AUDIO3_MERR_IRQ,
|
||||
MACEISA_RTC_IRQ,
|
||||
MACEISA_KEYB_IRQ,
|
||||
/* MACEISA_KEYB_POLL is not an IRQ */
|
||||
__MACEISA_KEYB_POLL,
|
||||
MACEISA_MOUSE_IRQ,
|
||||
/* MACEISA_MOUSE_POLL is not an IRQ */
|
||||
__MACEISA_MOUSE_POLL,
|
||||
MACEISA_TIMER0_IRQ,
|
||||
MACEISA_TIMER1_IRQ,
|
||||
MACEISA_TIMER2_IRQ,
|
||||
MACEISA_PARALLEL_IRQ,
|
||||
MACEISA_PAR_CTXA_IRQ,
|
||||
MACEISA_PAR_CTXB_IRQ,
|
||||
MACEISA_PAR_MERR_IRQ,
|
||||
MACEISA_SERIAL1_IRQ,
|
||||
MACEISA_SERIAL1_TDMAT_IRQ,
|
||||
MACEISA_SERIAL1_TDMAPR_IRQ,
|
||||
MACEISA_SERIAL1_TDMAME_IRQ,
|
||||
MACEISA_SERIAL1_RDMAT_IRQ,
|
||||
MACEISA_SERIAL1_RDMAOR_IRQ,
|
||||
MACEISA_SERIAL2_IRQ,
|
||||
MACEISA_SERIAL2_TDMAT_IRQ,
|
||||
MACEISA_SERIAL2_TDMAPR_IRQ,
|
||||
MACEISA_SERIAL2_TDMAME_IRQ,
|
||||
MACEISA_SERIAL2_RDMAT_IRQ,
|
||||
MACEISA_SERIAL2_RDMAOR_IRQ,
|
||||
|
||||
#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
|
||||
IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
|
||||
};
|
||||
|
||||
#endif /* __ASM_IP32_INTS_H */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,10 @@
|
|||
#define LASATINT_END 16
|
||||
#ifndef __ASM_LASAT_LASATINT_H
|
||||
#define __ASM_LASAT_LASATINT_H
|
||||
|
||||
#include <linux/irq.h>
|
||||
|
||||
#define LASATINT_BASE MIPS_CPU_IRQ_BASE
|
||||
#define LASATINT_END (LASATINT_BASE + 16)
|
||||
|
||||
/* lasat 100 */
|
||||
#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
|
||||
|
|
@ -10,3 +16,4 @@
|
|||
#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
|
||||
#define LASATINT_MASK_SHIFT_200 16
|
||||
|
||||
#endif /* __ASM_LASAT_LASATINT_H */
|
||||
|
|
|
|||
|
|
@ -91,23 +91,6 @@ static inline u32 au_readl(unsigned long reg)
|
|||
}
|
||||
|
||||
|
||||
static __inline__ int au_ffz(unsigned int x)
|
||||
{
|
||||
if ((x = ~x) == 0)
|
||||
return 32;
|
||||
return __ilog2(x & -x);
|
||||
}
|
||||
|
||||
/*
|
||||
* ffs: find first bit set. This is defined the same way as
|
||||
* the libc and compiler builtin ffs routines, therefore
|
||||
* differs in spirit from the above ffz (man ffs).
|
||||
*/
|
||||
static __inline__ int au_ffs(int x)
|
||||
{
|
||||
return __ilog2(x & -x) + 1;
|
||||
}
|
||||
|
||||
/* arch/mips/au1000/common/clocks.c */
|
||||
extern void set_au1x00_speed(unsigned int new_freq);
|
||||
extern unsigned int get_au1x00_speed(void);
|
||||
|
|
@ -119,16 +102,16 @@ extern unsigned int get_au1x00_lcd_clock(void);
|
|||
/*
|
||||
* Every board describes its IRQ mapping with this table.
|
||||
*/
|
||||
typedef struct au1xxx_irqmap {
|
||||
struct au1xxx_irqmap {
|
||||
int im_irq;
|
||||
int im_type;
|
||||
int im_request;
|
||||
} au1xxx_irq_map_t;
|
||||
};
|
||||
|
||||
/*
|
||||
* init_IRQ looks for a table with this name.
|
||||
*/
|
||||
extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
extern struct au1xxx_irqmap au1xxx_irq_map[];
|
||||
|
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
|
||||
#define __ASM_MIPS_PMC_SIERRA_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
|
||||
defined(CONFIG_PMC_MSP7120_FPGA)
|
||||
#define MIPS34K_MISSED_ITLB_WAR 1
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
|
||||
|
|
@ -86,9 +86,9 @@ struct pt_regs {
|
|||
|
||||
extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
|
||||
|
||||
extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
|
||||
extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET;
|
||||
|
||||
static inline void die_if_kernel(const char *str, struct pt_regs *regs)
|
||||
static inline void die_if_kernel(const char *str, const struct pt_regs *regs)
|
||||
{
|
||||
if (unlikely(!user_mode(regs)))
|
||||
die(str, regs);
|
||||
|
|
|
|||
Loading…
Reference in New Issue