arm64: Sort vendor-specific errata
Sort configuration options for vendor-specific errata by vendor, to increase uniformity. Move ARM64_WORKAROUND_REPEAT_TLBI up, as it is also selected by ARM64_ERRATUM_1286807. Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Will Deacon <will@kernel.org>
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@ -553,6 +553,9 @@ config ARM64_ERRATUM_1530923
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If unsure, say Y.
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config ARM64_WORKAROUND_REPEAT_TLBI
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bool
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config ARM64_ERRATUM_1286807
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bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
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default y
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@ -694,6 +697,35 @@ config CAVIUM_TX2_ERRATUM_219
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If unsure, say Y.
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config FUJITSU_ERRATUM_010001
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bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
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default y
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help
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This option adds a workaround for Fujitsu-A64FX erratum E#010001.
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On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
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accesses may cause undefined fault (Data abort, DFSC=0b111111).
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This fault occurs under a specific hardware condition when a
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load/store instruction performs an address translation using:
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case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
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case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
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case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
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case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
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The workaround is to ensure these bits are clear in TCR_ELx.
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The workaround only affects the Fujitsu-A64FX.
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If unsure, say Y.
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config HISILICON_ERRATUM_161600802
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bool "Hip07 161600802: Erroneous redistributor VLPI base"
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default y
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help
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The HiSilicon Hip07 SoC uses the wrong redistributor base
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when issued ITS commands such as VMOVP and VMAPP, and requires
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a 128kB offset to be applied to the target address in this commands.
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If unsure, say Y.
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config QCOM_FALKOR_ERRATUM_1003
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bool "Falkor E1003: Incorrect translation due to ASID change"
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default y
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@ -705,9 +737,6 @@ config QCOM_FALKOR_ERRATUM_1003
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is unchanged. Work around the erratum by invalidating the walk cache
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entries for the trampoline before entering the kernel proper.
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config ARM64_WORKAROUND_REPEAT_TLBI
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bool
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config QCOM_FALKOR_ERRATUM_1009
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bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
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default y
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@ -729,25 +758,6 @@ config QCOM_QDF2400_ERRATUM_0065
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If unsure, say Y.
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config SOCIONEXT_SYNQUACER_PREITS
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bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
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default y
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help
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Socionext Synquacer SoCs implement a separate h/w block to generate
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MSI doorbell writes with non-zero values for the device ID.
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If unsure, say Y.
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config HISILICON_ERRATUM_161600802
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bool "Hip07 161600802: Erroneous redistributor VLPI base"
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default y
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help
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The HiSilicon Hip07 SoC uses the wrong redistributor base
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when issued ITS commands such as VMOVP and VMAPP, and requires
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a 128kB offset to be applied to the target address in this commands.
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If unsure, say Y.
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config QCOM_FALKOR_ERRATUM_E1041
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bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
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default y
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@ -758,22 +768,12 @@ config QCOM_FALKOR_ERRATUM_E1041
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If unsure, say Y.
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config FUJITSU_ERRATUM_010001
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bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
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config SOCIONEXT_SYNQUACER_PREITS
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bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
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default y
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help
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This option adds a workaround for Fujitsu-A64FX erratum E#010001.
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On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
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accesses may cause undefined fault (Data abort, DFSC=0b111111).
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This fault occurs under a specific hardware condition when a
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load/store instruction performs an address translation using:
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case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
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case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
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case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
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case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
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The workaround is to ensure these bits are clear in TCR_ELx.
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The workaround only affects the Fujitsu-A64FX.
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Socionext Synquacer SoCs implement a separate h/w block to generate
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MSI doorbell writes with non-zero values for the device ID.
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If unsure, say Y.
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