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MLK-22445-2 ARM64: dts: imx8-ss-conn: add Cadence USB3 support 

Add Cadence USB3 support

Signed-off-by: Peter Chen <peter.chen@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Peter Chen 2019-08-15 17:20:47 +08:00 committed by Dong Aisheng
parent 12447ceff9
commit ec1a037c5f
1 changed files with 49 additions and 0 deletions
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49
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
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@ -154,6 +154,35 @@ conn_subsys: bus@5b000000 {
status = "disabled";
};
usb3phynop1: usb3-phy {
compatible = "usb-nop-xceiv";
clocks = <&usb3_lpcg 4>;
clock-names = "main_clk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
status = "disabled";
};
usbotg3: usb3@5b110000 {
compatible = "Cadence,usb3";
reg = <0x5B110000 0x10000>,
<0x5B130000 0x10000>,
<0x5B140000 0x10000>,
<0x5B160000 0x40000>,
<0x5B120000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb3_lpcg 1>,
<&usb3_lpcg 0>,
<&usb3_lpcg 5>,
<&usb3_lpcg 2>,
<&usb3_lpcg 3>;
clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
"usb3_ipg_clk", "usb3_core_pclk";
power-domains = <&pd IMX_SC_R_USB_2>;
cdns3,usbphy = <&usb3phynop1>;
status = "disabled";
};
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
@ -244,4 +273,24 @@ conn_subsys: bus@5b000000 {
"usboh3_phy_ipg_clk";
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
};
usb3_lpcg: clock-controller@5b280000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b280000 0x10000>;
#clock-cells = <1>;
bit-offset = <0 4 16 20 24 28>;
clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
<&conn_ipg_clk>,
<&conn_ipg_clk>,
<&conn_ipg_clk>,
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
clock-output-names = "usb3_app_clk",
"usb3_lpm_clk",
"usb3_ipg_clk",
"usb3_core_pclk",
"usb3_phy_clk",
"usb3_aclk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
};
};