From ec7aaca2f64f509f45d463d784b41d0b3d2be083 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 13 Jun 2012 15:42:36 +0530 Subject: [PATCH] i2c: tegra: make sure register writes completes The Tegra PPSB (an peripheral bus) queues writes transactions. In order to guarantee that writes have completed before a certain time, a read transaction to a register on the same bus must be executed. This is necessary in situations such as when clearing an interrupt status or enable, so that when returning from an interrupt handler, the HW has already de-asserted its interrupt status output, which will avoid spurious interrupts. Signed-off-by: Laxman Dewangan Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 8b2e555a9563..785f7f7a344a 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -165,6 +165,10 @@ static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) { writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); + + /* Read back register to make sure that register writes completed */ + if (reg != I2C_TX_FIFO) + readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); } static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)