serial: msm: Add support for UARTDM cores
Add support for the next-generation version of the MSM UART to the msm_serial driver. This version of the hardware is similar to the original version, but has some DMA capabilities that are used in PIO mode in this driver. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
Stepan Moskovchenko
David Brown
parent
d41cb8c956
commit
ec8f29e70e
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Robert Love <rlove@google.com>
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -31,6 +32,7 @@
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#include <linux/serial.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include "msm_serial.h"
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@ -38,9 +40,20 @@ struct msm_port {
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struct uart_port uart;
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char name[16];
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struct clk *clk;
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struct clk *pclk;
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unsigned int imr;
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unsigned int *gsbi_base;
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int is_uartdm;
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unsigned int old_snap_state;
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};
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static inline void wait_for_xmitr(struct uart_port *port, int bits)
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{
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if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
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while ((msm_read(port, UART_ISR) & bits) != bits)
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cpu_relax();
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}
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static void msm_stop_tx(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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@ -73,6 +86,61 @@ static void msm_enable_ms(struct uart_port *port)
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msm_write(port, msm_port->imr, UART_IMR);
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}
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static void handle_rx_dm(struct uart_port *port, unsigned int misr)
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{
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struct tty_struct *tty = port->state->port.tty;
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unsigned int sr;
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int count = 0;
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struct msm_port *msm_port = UART_TO_MSM(port);
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if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
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port->icount.overrun++;
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
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}
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if (misr & UART_IMR_RXSTALE) {
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count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
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msm_port->old_snap_state;
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msm_port->old_snap_state = 0;
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} else {
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count = 4 * (msm_read(port, UART_RFWR));
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msm_port->old_snap_state += count;
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}
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/* TODO: Precise error reporting */
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port->icount.rx += count;
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while (count > 0) {
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unsigned int c;
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sr = msm_read(port, UART_SR);
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if ((sr & UART_SR_RX_READY) == 0) {
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msm_port->old_snap_state -= count;
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break;
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}
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c = msm_read(port, UARTDM_RF);
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if (sr & UART_SR_RX_BREAK) {
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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} else if (sr & UART_SR_PAR_FRAME_ERR)
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port->icount.frame++;
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/* TODO: handle sysrq */
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tty_insert_flip_string(tty, (char *) &c,
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(count > 4) ? 4 : count);
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count -= 4;
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}
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tty_flip_buffer_push(tty);
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if (misr & (UART_IMR_RXSTALE))
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msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
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msm_write(port, 0xFFFFFF, UARTDM_DMRX);
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msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
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}
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static void handle_rx(struct uart_port *port)
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{
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struct tty_struct *tty = port->state->port.tty;
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@ -121,6 +189,12 @@ static void handle_rx(struct uart_port *port)
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tty_flip_buffer_push(tty);
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}
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static void reset_dm_count(struct uart_port *port)
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{
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wait_for_xmitr(port, UART_ISR_TX_READY);
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msm_write(port, 1, UARTDM_NCF_TX);
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}
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static void handle_tx(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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@ -128,11 +202,18 @@ static void handle_tx(struct uart_port *port)
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int sent_tx;
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if (port->x_char) {
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msm_write(port, port->x_char, UART_TF);
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if (msm_port->is_uartdm)
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reset_dm_count(port);
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msm_write(port, port->x_char,
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msm_port->is_uartdm ? UARTDM_TF : UART_TF);
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port->icount.tx++;
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port->x_char = 0;
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}
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if (msm_port->is_uartdm)
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reset_dm_count(port);
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while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
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if (uart_circ_empty(xmit)) {
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/* disable tx interrupts */
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@ -140,8 +221,11 @@ static void handle_tx(struct uart_port *port)
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msm_write(port, msm_port->imr, UART_IMR);
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break;
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}
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msm_write(port, xmit->buf[xmit->tail],
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msm_port->is_uartdm ? UARTDM_TF : UART_TF);
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msm_write(port, xmit->buf[xmit->tail], UART_TF);
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if (msm_port->is_uartdm)
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reset_dm_count(port);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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@ -169,8 +253,12 @@ static irqreturn_t msm_irq(int irq, void *dev_id)
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misr = msm_read(port, UART_MISR);
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msm_write(port, 0, UART_IMR); /* disable interrupt */
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if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE))
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handle_rx(port);
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if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
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if (msm_port->is_uartdm)
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handle_rx_dm(port, misr);
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else
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handle_rx(port);
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}
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if (misr & UART_IMR_TXLEV)
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handle_tx(port);
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if (misr & UART_IMR_DELTA_CTS)
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@ -192,10 +280,21 @@ static unsigned int msm_get_mctrl(struct uart_port *port)
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return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
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}
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static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
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static void msm_reset(struct uart_port *port)
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{
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/* reset everything */
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msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
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msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
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}
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void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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unsigned int mr;
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mr = msm_read(port, UART_MR1);
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if (!(mctrl & TIOCM_RTS)) {
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@ -219,6 +318,7 @@ static void msm_break_ctl(struct uart_port *port, int break_ctl)
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static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
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{
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unsigned int baud_code, rxstale, watermark;
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struct msm_port *msm_port = UART_TO_MSM(port);
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switch (baud) {
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case 300:
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@ -273,6 +373,9 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
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break;
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}
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if (msm_port->is_uartdm)
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msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
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msm_write(port, baud_code, UART_CSR);
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/* RX stale watermark */
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@ -288,25 +391,23 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
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/* set TX watermark */
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msm_write(port, 10, UART_TFWR);
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if (msm_port->is_uartdm) {
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msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
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msm_write(port, 0xFFFFFF, UARTDM_DMRX);
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msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
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}
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return baud;
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}
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static void msm_reset(struct uart_port *port)
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{
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/* reset everything */
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msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
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msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
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}
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static void msm_init_clock(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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clk_enable(msm_port->clk);
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if (!IS_ERR(msm_port->pclk))
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clk_enable(msm_port->pclk);
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msm_serial_set_mnd_regs(port);
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}
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@ -347,15 +448,31 @@ static int msm_startup(struct uart_port *port)
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msm_write(port, data, UART_IPR);
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}
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msm_reset(port);
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data = 0;
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if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
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msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
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msm_reset(port);
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data = UART_CR_TX_ENABLE;
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}
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msm_write(port, 0x05, UART_CR); /* enable TX & RX */
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data |= UART_CR_RX_ENABLE;
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msm_write(port, data, UART_CR); /* enable TX & RX */
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/* Make sure IPR is not 0 to start with*/
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if (msm_port->is_uartdm)
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msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
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/* turn on RX and CTS interrupts */
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msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
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UART_IMR_CURRENT_CTS;
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msm_write(port, msm_port->imr, UART_IMR);
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if (msm_port->is_uartdm) {
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msm_write(port, 0xFFFFFF, UARTDM_DMRX);
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msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
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msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
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}
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msm_write(port, msm_port->imr, UART_IMR);
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return 0;
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}
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@ -384,7 +501,7 @@ static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
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baud = msm_set_baud_rate(port, baud);
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if (tty_termios_baud_rate(termios))
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tty_termios_encode_baud_rate(termios, baud, baud);
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/* calculate parity */
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mr = msm_read(port, UART_MR2);
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mr &= ~UART_MR2_PARITY_MODE;
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@ -454,48 +571,105 @@ static const char *msm_type(struct uart_port *port)
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static void msm_release_port(struct uart_port *port)
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{
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struct platform_device *pdev = to_platform_device(port->dev);
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struct resource *resource;
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struct msm_port *msm_port = UART_TO_MSM(port);
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struct resource *uart_resource;
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struct resource *gsbi_resource;
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resource_size_t size;
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resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!resource))
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uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!uart_resource))
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return;
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size = resource->end - resource->start + 1;
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size = resource_size(uart_resource);
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release_mem_region(port->mapbase, size);
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iounmap(port->membase);
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port->membase = NULL;
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if (msm_port->gsbi_base) {
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iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
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GSBI_CONTROL);
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gsbi_resource = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"gsbi_resource");
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if (unlikely(!gsbi_resource))
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return;
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size = resource_size(gsbi_resource);
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release_mem_region(gsbi_resource->start, size);
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iounmap(msm_port->gsbi_base);
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msm_port->gsbi_base = NULL;
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}
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}
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static int msm_request_port(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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struct platform_device *pdev = to_platform_device(port->dev);
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struct resource *resource;
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struct resource *uart_resource;
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struct resource *gsbi_resource;
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resource_size_t size;
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int ret;
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resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!resource))
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uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"uart_resource");
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if (unlikely(!uart_resource))
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return -ENXIO;
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size = resource->end - resource->start + 1;
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if (unlikely(!request_mem_region(port->mapbase, size, "msm_serial")))
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size = resource_size(uart_resource);
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if (!request_mem_region(port->mapbase, size, "msm_serial"))
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return -EBUSY;
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port->membase = ioremap(port->mapbase, size);
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if (!port->membase) {
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release_mem_region(port->mapbase, size);
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return -EBUSY;
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ret = -EBUSY;
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goto fail_release_port;
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}
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gsbi_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"gsbi_resource");
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/* Is this a GSBI-based port? */
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if (gsbi_resource) {
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size = resource_size(gsbi_resource);
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if (!request_mem_region(gsbi_resource->start, size,
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"msm_serial")) {
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ret = -EBUSY;
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goto fail_release_port;
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}
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msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
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if (!msm_port->gsbi_base) {
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ret = -EBUSY;
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goto fail_release_gsbi;
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}
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}
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return 0;
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fail_release_gsbi:
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release_mem_region(gsbi_resource->start, size);
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fail_release_port:
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release_mem_region(port->mapbase, size);
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return ret;
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}
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static void msm_config_port(struct uart_port *port, int flags)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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int ret;
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if (flags & UART_CONFIG_TYPE) {
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port->type = PORT_MSM;
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msm_request_port(port);
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ret = msm_request_port(port);
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if (ret)
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return;
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}
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if (msm_port->is_uartdm)
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iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
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GSBI_CONTROL);
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}
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static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
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@ -515,9 +689,13 @@ static void msm_power(struct uart_port *port, unsigned int state,
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switch (state) {
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case 0:
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clk_enable(msm_port->clk);
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if (!IS_ERR(msm_port->pclk))
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clk_enable(msm_port->pclk);
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break;
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case 3:
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clk_disable(msm_port->clk);
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if (!IS_ERR(msm_port->pclk))
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clk_disable(msm_port->pclk);
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break;
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default:
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printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
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@ -550,7 +728,7 @@ static struct msm_port msm_uart_ports[] = {
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.iotype = UPIO_MEM,
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.ops = &msm_uart_pops,
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.flags = UPF_BOOT_AUTOCONF,
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.fifosize = 512,
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.fifosize = 64,
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.line = 0,
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},
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},
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@ -559,7 +737,7 @@ static struct msm_port msm_uart_ports[] = {
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|||
.iotype = UPIO_MEM,
|
||||
.ops = &msm_uart_pops,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.fifosize = 512,
|
||||
.fifosize = 64,
|
||||
.line = 1,
|
||||
},
|
||||
},
|
||||
|
|
@ -585,9 +763,14 @@ static inline struct uart_port *get_port_from_line(unsigned int line)
|
|||
|
||||
static void msm_console_putchar(struct uart_port *port, int c)
|
||||
{
|
||||
struct msm_port *msm_port = UART_TO_MSM(port);
|
||||
|
||||
if (msm_port->is_uartdm)
|
||||
reset_dm_count(port);
|
||||
|
||||
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
|
||||
;
|
||||
msm_write(port, c, UART_TF);
|
||||
msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
|
||||
}
|
||||
|
||||
static void msm_console_write(struct console *co, const char *s,
|
||||
|
|
@ -609,12 +792,14 @@ static void msm_console_write(struct console *co, const char *s,
|
|||
static int __init msm_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct uart_port *port;
|
||||
struct msm_port *msm_port;
|
||||
int baud, flow, bits, parity;
|
||||
|
||||
if (unlikely(co->index >= UART_NR || co->index < 0))
|
||||
return -ENXIO;
|
||||
|
||||
port = get_port_from_line(co->index);
|
||||
msm_port = UART_TO_MSM(port);
|
||||
|
||||
if (unlikely(!port->membase))
|
||||
return -ENXIO;
|
||||
|
|
@ -638,6 +823,11 @@ static int __init msm_console_setup(struct console *co, char *options)
|
|||
|
||||
msm_reset(port);
|
||||
|
||||
if (msm_port->is_uartdm) {
|
||||
msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
|
||||
msm_write(port, UART_CR_TX_ENABLE, UART_CR);
|
||||
}
|
||||
|
||||
printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
|
||||
|
||||
return uart_set_options(port, co, baud, parity, bits, flow);
|
||||
|
|
@ -685,14 +875,32 @@ static int __init msm_serial_probe(struct platform_device *pdev)
|
|||
port->dev = &pdev->dev;
|
||||
msm_port = UART_TO_MSM(port);
|
||||
|
||||
msm_port->clk = clk_get(&pdev->dev, "uart_clk");
|
||||
if (IS_ERR(msm_port->clk))
|
||||
return PTR_ERR(msm_port->clk);
|
||||
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsbi_resource"))
|
||||
msm_port->is_uartdm = 1;
|
||||
else
|
||||
msm_port->is_uartdm = 0;
|
||||
|
||||
if (msm_port->is_uartdm) {
|
||||
msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
|
||||
msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
|
||||
} else {
|
||||
msm_port->clk = clk_get(&pdev->dev, "uart_clk");
|
||||
msm_port->pclk = ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) &&
|
||||
msm_port->is_uartdm)))
|
||||
return PTR_ERR(msm_port->clk);
|
||||
|
||||
if (msm_port->is_uartdm)
|
||||
clk_set_rate(msm_port->clk, 7372800);
|
||||
|
||||
port->uartclk = clk_get_rate(msm_port->clk);
|
||||
printk(KERN_INFO "uartclk = %d\n", port->uartclk);
|
||||
|
||||
|
||||
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"uart_resource");
|
||||
if (unlikely(!resource))
|
||||
return -ENXIO;
|
||||
port->mapbase = resource->start;
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Author: Robert Love <rlove@google.com>
|
||||
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
|
@ -54,6 +55,7 @@
|
|||
#define UART_CSR_300 0x22
|
||||
|
||||
#define UART_TF 0x000C
|
||||
#define UARTDM_TF 0x0070
|
||||
|
||||
#define UART_CR 0x0010
|
||||
#define UART_CR_CMD_NULL (0 << 4)
|
||||
|
|
@ -64,14 +66,17 @@
|
|||
#define UART_CR_CMD_START_BREAK (5 << 4)
|
||||
#define UART_CR_CMD_STOP_BREAK (6 << 4)
|
||||
#define UART_CR_CMD_RESET_CTS (7 << 4)
|
||||
#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
|
||||
#define UART_CR_CMD_PACKET_MODE (9 << 4)
|
||||
#define UART_CR_CMD_MODE_RESET (12 << 4)
|
||||
#define UART_CR_CMD_SET_RFR (13 << 4)
|
||||
#define UART_CR_CMD_RESET_RFR (14 << 4)
|
||||
#define UART_CR_CMD_PROTECTION_EN (16 << 4)
|
||||
#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
|
||||
#define UART_CR_TX_DISABLE (1 << 3)
|
||||
#define UART_CR_TX_ENABLE (1 << 3)
|
||||
#define UART_CR_RX_DISABLE (1 << 3)
|
||||
#define UART_CR_RX_ENABLE (1 << 3)
|
||||
#define UART_CR_TX_ENABLE (1 << 2)
|
||||
#define UART_CR_RX_DISABLE (1 << 1)
|
||||
#define UART_CR_RX_ENABLE (1 << 0)
|
||||
|
||||
#define UART_IMR 0x0014
|
||||
#define UART_IMR_TXLEV (1 << 0)
|
||||
|
|
@ -110,9 +115,20 @@
|
|||
#define UART_SR_RX_FULL (1 << 1)
|
||||
#define UART_SR_RX_READY (1 << 0)
|
||||
|
||||
#define UART_RF 0x000C
|
||||
#define UART_MISR 0x0010
|
||||
#define UART_ISR 0x0014
|
||||
#define UART_RF 0x000C
|
||||
#define UARTDM_RF 0x0070
|
||||
#define UART_MISR 0x0010
|
||||
#define UART_ISR 0x0014
|
||||
#define UART_ISR_TX_READY (1 << 7)
|
||||
|
||||
#define GSBI_CONTROL 0x0
|
||||
#define GSBI_PROTOCOL_CODE 0x30
|
||||
#define GSBI_PROTOCOL_UART 0x40
|
||||
#define GSBI_PROTOCOL_IDLE 0x0
|
||||
|
||||
#define UARTDM_DMRX 0x34
|
||||
#define UARTDM_NCF_TX 0x40
|
||||
#define UARTDM_RX_TOTAL_SNAP 0x38
|
||||
|
||||
#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue