redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

drm/nve0/graph: fix fuc, and enable acceleration on all known chipsets

Browse source 
Also adds GK106 to chipsets known by ucode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-12-20 12:52:06 +10:00
parent 902530693e
commit eca15296a9
5 changed files with 108 additions and 86 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
View file

@ -57,6 +57,11 @@ chipsets:
.b16 #nve4_gpc_mmio_tail .b16 #nve4_gpc_mmio_tail
.b16 #nve4_tpc_mmio_head .b16 #nve4_tpc_mmio_head
.b16 #nve4_tpc_mmio_tail .b16 #nve4_tpc_mmio_tail
.b8 0xe6 0 0 0
.b16 #nve4_gpc_mmio_head
.b16 #nve4_gpc_mmio_tail
.b16 #nve4_tpc_mmio_head
.b16 #nve4_tpc_mmio_tail
.b8 0 0 0 0 .b8 0 0 0 0
// GPC mmio lists // GPC mmio lists

17
drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
View file

@ -34,13 +34,16 @@ uint32_t nve0_grgpc_data[] = {
0x00000000, 0x00000000,
/* 0x0064: chipsets */ /* 0x0064: chipsets */
0x000000e4, 0x000000e4,
0x01040080, 0x0110008c,
0x014c0104, 0x01580110,
0x000000e7, 0x000000e7,
0x01040080, 0x0110008c,
0x014c0104, 0x01580110,
0x000000e6,
0x0110008c,
0x01580110,
0x00000000, 0x00000000,
/* 0x0080: nve4_gpc_mmio_head */ /* 0x008c: nve4_gpc_mmio_head */
0x00000380, 0x00000380,
0x04000400, 0x04000400,
0x0800040c, 0x0800040c,
@ -74,8 +77,8 @@ uint32_t nve0_grgpc_data[] = {
0x14003100, 0x14003100,
0x000031d0, 0x000031d0,
0x040031e0, 0x040031e0,
/* 0x0104: nve4_gpc_mmio_tail */ /* 0x0110: nve4_gpc_mmio_tail */
/* 0x0104: nve4_tpc_mmio_head */ /* 0x0110: nve4_tpc_mmio_head */
0x00000048, 0x00000048,
0x00000064, 0x00000064,
0x00000088, 0x00000088,

13
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
View file

@ -44,6 +44,9 @@ chipsets:
.b8 0xe7 0 0 0 .b8 0xe7 0 0 0
.b16 #nve4_hub_mmio_head .b16 #nve4_hub_mmio_head
.b16 #nve4_hub_mmio_tail .b16 #nve4_hub_mmio_tail
.b8 0xe6 0 0 0
.b16 #nve4_hub_mmio_head
.b16 #nve4_hub_mmio_tail
.b8 0 0 0 0 .b8 0 0 0 0
nve4_hub_mmio_head: nve4_hub_mmio_head:
@ -680,6 +683,16 @@ ctx_mmio_exec:
// on load it means: "a save preceeded this load" // on load it means: "a save preceeded this load"
// //
ctx_xfer: ctx_xfer:
// according to mwk, some kind of wait for idle
mov $r15 0xc00
shl b32 $r15 6
mov $r14 4
iowr I[$r15 + 0x200] $r14
ctx_xfer_idle:
iord $r14 I[$r15 + 0x000]
and $r14 0x2000
bra ne #ctx_xfer_idle
bra not $p1 #ctx_xfer_pre bra not $p1 #ctx_xfer_pre
bra $p2 #ctx_xfer_pre_load bra $p2 #ctx_xfer_pre_load
ctx_xfer_pre: ctx_xfer_pre:

157
drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
View file

@ -30,11 +30,13 @@ uint32_t nve0_grhub_data[] = {
0x00000000, 0x00000000,
/* 0x005c: chipsets */ /* 0x005c: chipsets */
0x000000e4, 0x000000e4,
0x013c0070, 0x01440078,
0x000000e7, 0x000000e7,
0x013c0070, 0x01440078,
0x000000e6,
0x01440078,
0x00000000, 0x00000000,
/* 0x0070: nve4_hub_mmio_head */ /* 0x0078: nve4_hub_mmio_head */
0x0417e91c, 0x0417e91c,
0x04400204, 0x04400204,
0x18404010, 0x18404010,
@ -86,9 +88,7 @@ uint32_t nve0_grhub_data[] = {
0x00408840, 0x00408840,
0x08408900, 0x08408900,
0x00408980, 0x00408980,
/* 0x013c: nve4_hub_mmio_tail */ /* 0x0144: nve4_hub_mmio_tail */
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
@ -781,77 +781,78 @@ uint32_t nve0_grhub_code[] = {
0x0613f002, 0x0613f002,
0xf80601fa, 0xf80601fa,
/* 0x07fb: ctx_xfer */ /* 0x07fb: ctx_xfer */
0xf400f803, 0xf100f803,
0x02f40611, 0xb60c00f7,
/* 0x0801: ctx_xfer_pre */ 0xe7f006f4,
0x10f7f00d, 0x80fed004,
0x067221f5, /* 0x0808: ctx_xfer_idle */
/* 0x080b: ctx_xfer_pre_load */ 0xf100fecf,
0xf01c11f4, 0xf42000e4,
0x21f502f7, 0x11f4f91b,
0x21f50631, 0x0d02f406,
0x21f50640, /* 0x0818: ctx_xfer_pre */
0xf4bd0652, 0xf510f7f0,
0x063121f5, 0xf4067221,
0x069221f5, /* 0x0822: ctx_xfer_pre_load */
/* 0x0824: ctx_xfer_exec */ 0xf7f01c11,
0xf1160198, 0x3121f502,
0xb6041427, 0x4021f506,
0x20d00624, 0x5221f506,
0x00e7f100, 0xf5f4bd06,
0x41e3f0a5, 0xf5063121,
0xf4021fb9, /* 0x083b: ctx_xfer_exec */
0xe0b68d21, 0x98069221,
0x01fcf004, 0x27f11601,
0xb6022cf0, 0x24b60414,
0xf2fd0124, 0x0020d006,
0x8d21f405, 0xa500e7f1,
0x4afc17f1, 0xb941e3f0,
0xf00213f0, 0x21f4021f,
0x12d00c27, 0x04e0b68d,
0x0721f500, 0xf001fcf0,
0xfc27f102, 0x24b6022c,
0x0223f047, 0x05f2fd01,
0xf00020d0, 0xf18d21f4,
0x20b6012c, 0xf04afc17,
0x0012d003, 0x27f00213,
0xf001acf0, 0x0012d00c,
0xb7f006a5, 0x020721f5,
0x140c9800, 0x47fc27f1,
0xf0150d98, 0xd00223f0,
0x21f500e7, 0x2cf00020,
0xa7f0015c, 0x0320b601,
0x0321f508, 0xf00012d0,
0x0721f501, 0xa5f001ac,
0x2201f402, 0x00b7f006,
0xf40ca7f0, 0x98140c98,
0x17f1c921, 0xe7f0150d,
0x14b60a10, 0x5c21f500,
0x0527f006, 0x08a7f001,
/* 0x08ab: ctx_xfer_post_save_wait */ 0x010321f5,
0xcf0012d0, 0x020721f5,
0x22fd0012, 0xf02201f4,
0xfa1bf405, 0x21f40ca7,
/* 0x08b7: ctx_xfer_post */ 0x1017f1c9,
0xf02e02f4, 0x0614b60a,
0x21f502f7, 0xd00527f0,
0xf4bd0631, /* 0x08c2: ctx_xfer_post_save_wait */
0x067221f5, 0x12cf0012,
0x022621f5, 0x0522fd00,
0x064021f5, 0xf4fa1bf4,
0x21f5f4bd, /* 0x08ce: ctx_xfer_post */
0x11f40631, 0xf7f02e02,
0x80019810, 0x3121f502,
0xf40511fd, 0xf5f4bd06,
0x21f5070b, 0xf5067221,
/* 0x08e2: ctx_xfer_no_post_mmio */ 0xf5022621,
/* 0x08e2: ctx_xfer_done */ 0xbd064021,
0x00f807b1, 0x3121f5f4,
0x00000000, 0x1011f406,
0x00000000, 0xfd800198,
0x00000000, 0x0bf40511,
0x00000000, 0xb121f507,
0x00000000, /* 0x08f9: ctx_xfer_no_post_mmio */
0x00000000, /* 0x08f9: ctx_xfer_done */
0x0000f807,
0x00000000, 0x00000000,
}; };

2
drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
View file

@ -203,7 +203,7 @@ nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nvc0_graph_priv *priv; struct nvc0_graph_priv *priv;
int ret, i; int ret, i;
ret = nouveau_graph_create(parent, engine, oclass, false, &priv); ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;