drm/amd/display: Add hubp block for Renoir (v2)
This provides the interface to memory for the display hw. v2: minor cleanup (Alex) Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>alistair/sunxi64-5.4-dsi
Bhawanpreet Lakha
Alex Deucher
parent
1e768c5b0f
commit
eced51f9ba
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#
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# Makefile for DCN21.
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DCN21 = dcn21_hubp.o
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CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
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AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
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AMD_DISPLAY_FILES += $(AMD_DAL_DCN21)
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@ -0,0 +1,244 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dcn21_hubp.h"
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#include "dm_services.h"
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#include "reg_helper.h"
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#define REG(reg)\
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hubp21->hubp_regs->reg
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#define CTX \
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hubp21->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
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/*
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* In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
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* As a result, if S/W updates any of these registers during a mode change,
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* the current frame before the mode change will use the new value right away
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* and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
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*
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* REFCYC_PER_VM_GROUP_FLIP[22:0]
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* REFCYC_PER_VM_GROUP_VBLANK[22:0]
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* REFCYC_PER_VM_REQ_FLIP[22:0]
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* REFCYC_PER_VM_REQ_VBLANK[22:0]
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*
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* REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
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* when flipping to a new surface
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*
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* REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
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* during prefetch period of a frame. The prefetch starts at a pre-determined
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* number of lines before the display active per frame
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*
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* DCN may underflow due to incorrectly programming these registers
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* during VM stage of prefetch/iflip. First lines of display active
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* or a sub-region of active using a new surface will be corrupted
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* until the VM data returns at flip/mode change transitions
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*
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* Work around:
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* workaround is always opt to use the more aggressive settings.
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* On any mode switch, if the new reg values are smaller than the current values,
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* then update the regs with the new values.
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*
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* Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
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*
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*/
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void apply_DEDCN21_142_wa_for_hostvm_deadline(
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struct hubp *hubp,
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struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
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{
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struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
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uint32_t cur_value;
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REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
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if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
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REG_SET(VBLANK_PARAMETERS_5, 0,
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REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
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REG_GET(VBLANK_PARAMETERS_6,
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REFCYC_PER_VM_REQ_VBLANK,
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&cur_value);
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if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
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REG_SET(VBLANK_PARAMETERS_6, 0,
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REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
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REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
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if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
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REG_SET(FLIP_PARAMETERS_3, 0,
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REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
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REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
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if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
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REG_SET(FLIP_PARAMETERS_4, 0,
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REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
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REG_SET(FLIP_PARAMETERS_5, 0,
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REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
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REG_SET(FLIP_PARAMETERS_6, 0,
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REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
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}
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void hubp21_program_deadline(
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struct hubp *hubp,
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struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
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struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
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{
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hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
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apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
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}
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void hubp21_program_requestor(
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struct hubp *hubp,
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struct _vcs_dpi_display_rq_regs_st *rq_regs)
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{
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struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
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REG_UPDATE(HUBPRET_CONTROL,
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DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
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REG_SET_4(DCN_EXPANSION_MODE, 0,
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DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
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PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
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MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
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CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
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REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
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CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
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MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
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META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
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MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
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DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
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VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
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SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
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PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
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REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
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CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
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MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
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META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
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MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
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DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
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SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
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PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
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}
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static void hubp21_setup(
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struct hubp *hubp,
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struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
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struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
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struct _vcs_dpi_display_rq_regs_st *rq_regs,
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struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
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{
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/* otg is locked when this func is called. Register are double buffered.
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* disable the requestors is not needed
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*/
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hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
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hubp21_program_requestor(hubp, rq_regs);
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hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
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}
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void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
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struct vm_system_aperture_param *apt)
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{
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struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
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PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
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PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
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PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
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// The format of default addr is 48:12 of the 48 bit addr
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mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
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// The format of high/low are 48:18 of the 48 bit addr
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mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
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mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
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REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
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MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
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REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
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MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
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REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
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ENABLE_L1_TLB, 1,
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SYSTEM_ACCESS_MODE, 0x3);
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}
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void hubp21_init(struct hubp *hubp)
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{
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// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
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// This is a chicken bit to enable the ECO fix.
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struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
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//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
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REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
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}
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static struct hubp_funcs dcn21_hubp_funcs = {
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.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
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.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
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.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
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.hubp_program_surface_config = hubp2_program_surface_config,
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.hubp_is_flip_pending = hubp1_is_flip_pending,
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.hubp_setup = hubp21_setup,
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.hubp_setup_interdependent = hubp2_setup_interdependent,
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.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
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.set_blank = hubp1_set_blank,
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.dcc_control = hubp1_dcc_control,
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.mem_program_viewport = min_set_viewport,
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.set_cursor_attributes = hubp2_cursor_set_attributes,
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.set_cursor_position = hubp1_cursor_set_position,
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.hubp_clk_cntl = hubp1_clk_cntl,
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.hubp_vtg_sel = hubp1_vtg_sel,
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.dmdata_set_attributes = hubp2_dmdata_set_attributes,
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.dmdata_load = hubp2_dmdata_load,
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.dmdata_status_done = hubp2_dmdata_status_done,
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.hubp_read_state = hubp1_read_state,
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.hubp_clear_underflow = hubp1_clear_underflow,
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.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
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.hubp_init = hubp21_init,
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};
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bool hubp21_construct(
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struct dcn21_hubp *hubp21,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn_hubp2_registers *hubp_regs,
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const struct dcn_hubp2_shift *hubp_shift,
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const struct dcn_hubp2_mask *hubp_mask)
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{
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hubp21->base.funcs = &dcn21_hubp_funcs;
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hubp21->base.ctx = ctx;
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hubp21->hubp_regs = hubp_regs;
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hubp21->hubp_shift = hubp_shift;
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hubp21->hubp_mask = hubp_mask;
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hubp21->base.inst = inst;
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hubp21->base.opp_id = OPP_ID_INVALID;
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hubp21->base.mpcc_id = 0xf;
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return true;
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}
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@ -0,0 +1,133 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DAL_DC_DCN21_DCN21_HUBP_H_
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#define DAL_DC_DCN21_DCN21_HUBP_H_
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#include "../dcn20/dcn20_hubp.h"
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#include "../dcn10/dcn10_hubp.h"
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#define TO_DCN21_HUBP(hubp)\
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container_of(hubp, struct dcn21_hubp, base)
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#define HUBP_REG_LIST_DCN21(id)\
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HUBP_REG_LIST_DCN2_COMMON(id),\
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SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\
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SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\
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SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\
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SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\
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SRI(VBLANK_PARAMETERS_6, HUBPREQ, id)
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#define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\
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HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
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HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
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HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
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HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
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HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
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HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
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HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
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HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
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HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
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HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
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HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
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HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
|
||||
|
||||
#define HUBP_MASK_SH_LIST_DCN21(mask_sh)\
|
||||
HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh)
|
||||
|
||||
|
||||
struct dcn21_hubp {
|
||||
struct hubp base;
|
||||
struct dcn_hubp_state state;
|
||||
const struct dcn_hubp2_registers *hubp_regs;
|
||||
const struct dcn_hubp2_shift *hubp_shift;
|
||||
const struct dcn_hubp2_mask *hubp_mask;
|
||||
};
|
||||
|
||||
bool hubp21_construct(
|
||||
struct dcn21_hubp *hubp21,
|
||||
struct dc_context *ctx,
|
||||
uint32_t inst,
|
||||
const struct dcn_hubp2_registers *hubp_regs,
|
||||
const struct dcn_hubp2_shift *hubp_shift,
|
||||
const struct dcn_hubp2_mask *hubp_mask);
|
||||
|
||||
void apply_DEDCN21_142_wa_for_hostvm_deadline(
|
||||
struct hubp *hubp,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_attr);
|
||||
|
||||
void hubp21_program_deadline(
|
||||
struct hubp *hubp,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
|
||||
|
||||
void hubp21_program_requestor(
|
||||
struct hubp *hubp,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs);
|
||||
#endif /* DAL_DC_DCN21_DCN21_HUBP_H_ */
|
||||
Loading…
Reference in New Issue