MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3
commit d191aaffe3
upstream.
LDDIR/LDPTE is Loongson-3's acceleration for Page Table Walking. If BD
(Base Directory, the 4th page directory) is not enabled, then GDOffset
is biased by BadVAddr[63:62]. So, if GDOffset (aka. BadVAddr[47:36] for
Loongson-3) is big enough, "0b11(BadVAddr[63:62])|BadVAddr[47:36]|...."
can far beyond pg_swapper_dir. This means the pg_swapper_dir may NOT be
accessed by LDDIR correctly, so fix it by set PWDirExt in CP0_PWCtl.
Cc: <stable@vger.kernel.org>
Signed-off-by: Pei Huang <huangpei@loongson.cn>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5.4-rM2-2.2.x-imx-squashed
parent
4acbbe98e0
commit
ed374eee8c
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@ -1480,6 +1480,7 @@ static void build_r4000_tlb_refill_handler(void)
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static void setup_pw(void)
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{
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unsigned int pwctl;
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unsigned long pgd_i, pgd_w;
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#ifndef __PAGETABLE_PMD_FOLDED
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unsigned long pmd_i, pmd_w;
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@ -1506,6 +1507,7 @@ static void setup_pw(void)
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pte_i = ilog2(_PAGE_GLOBAL);
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pte_w = 0;
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pwctl = 1 << 30; /* Set PWDirExt */
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#ifndef __PAGETABLE_PMD_FOLDED
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write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
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@ -1516,8 +1518,9 @@ static void setup_pw(void)
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#endif
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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write_c0_pwctl(1 << 6 | psn);
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pwctl |= (1 << 6 | psn);
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#endif
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write_c0_pwctl(pwctl);
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write_c0_kpgd((long)swapper_pg_dir);
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kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
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}
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