From ed49c29a999e381ccb30d94cdc144130bc50fe5b Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Thu, 8 Aug 2019 13:06:11 +0800 Subject: [PATCH] arm64: imx8-ss-dc0/1.dtsi: Add common dpu clocks Currently, all DPUs in i.MX8qm/qxp have the same clocks - pll0/1, bypass0 and disp0/1. So add the common clocks in imx8-ss-dc0/1.dtsi. Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi | 10 ---------- arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi | 5 ----- 4 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi index 6de96872c151..d18956d5c284 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -269,6 +269,12 @@ dc0_subsys: bus@56000000 { "framegen1_primsync_off", "framegen1_secsync_on", "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1"; power-domains = <&pd IMX_SC_R_DC_0>, <&pd IMX_SC_R_DC_0_PLL_0>, <&pd IMX_SC_R_DC_0_PLL_1>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index 550ce8204400..2716ca4a7c08 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -270,6 +270,12 @@ dc1_subsys: bus@57000000 { "framegen1_primsync_off", "framegen1_secsync_on", "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1"; power-domains = <&pd IMX_SC_R_DC_1>, <&pd IMX_SC_R_DC_1_PLL_0>, <&pd IMX_SC_R_DC_1_PLL_1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi index 83806ce59a47..d77a19f09ea5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi @@ -6,11 +6,6 @@ &dpu1 { compatible = "fsl,imx8qm-dpu"; - clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, - <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; - clock-names = "pll0", "pll1", "disp0", "disp1"; dpu1_disp0: port@0 { reg = <0>; @@ -31,11 +26,6 @@ &dpu2 { compatible = "fsl,imx8qm-dpu"; - clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, - <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; - clock-names = "pll0", "pll1", "disp0", "disp1"; dpu2_disp0: port@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi index 98530941c91d..aee2647a36dd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi @@ -6,11 +6,6 @@ &dpu1 { compatible = "fsl,imx8qxp-dpu"; - clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, - <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; - clock-names = "pll0", "pll1", "disp0", "disp1"; dpu_disp0: port@0 { reg = <0>;