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sh: sh7722 mode pin definitions 

This patch adds sh7722 mode pin and pin function
controller comments.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
hifive-unleashed-5.1
Magnus Damm 2009-06-03 08:18:56 +00:00 committed by Paul Mundt
parent 36e5b26bda
commit ed740cb9b7
1 changed files with 14 additions and 0 deletions
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14
arch/sh/include/cpu-sh4/cpu/sh7722.h
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@ -1,6 +1,20 @@
#ifndef __ASM_SH7722_H__
#define __ASM_SH7722_H__
/* Boot Mode Pins:
*
* MD0: CPG - Clock Mode 0->3
* MD1: CPG - Clock Mode 0->3
* MD2: CPG - Reserved (L: Normal operation)
* MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
* MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
* MD8: Test Mode
*/
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_Pxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* PTA */
GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,