fsi: master-gpio: Rename and adjust send delay
What the driver called "FSI_GPIO_PRIME_SLAVE_CLOCKS" is what the FSI spec calls tSendDelay and should be 16 clocks by default. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au>hifive-unleashed-5.1
parent
a2e7da86cc
commit
edc2485148
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@ -18,6 +18,7 @@
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#define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
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#define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
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#define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
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#define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
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#define FSI_SEND_DELAY_CLOCKS 16 /* Number clocks for send delay */
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#define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
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#define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
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#define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
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#define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
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#define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
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#define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
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@ -48,7 +49,6 @@
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#define FSI_GPIO_CRC_SIZE 4
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#define FSI_GPIO_CRC_SIZE 4
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#define FSI_GPIO_MSG_ID_SIZE 2
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#define FSI_GPIO_MSG_ID_SIZE 2
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#define FSI_GPIO_MSG_RESPID_SIZE 2
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#define FSI_GPIO_MSG_RESPID_SIZE 2
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#define FSI_GPIO_PRIME_SLAVE_CLOCKS 20
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#define LAST_ADDR_INVALID 0x1
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#define LAST_ADDR_INVALID 0x1
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@ -535,9 +535,12 @@ retry:
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if (busy_count > 0)
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if (busy_count > 0)
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trace_fsi_master_gpio_poll_response_busy(master, busy_count);
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trace_fsi_master_gpio_poll_response_busy(master, busy_count);
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fail:
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fail:
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/* Clock the slave enough to be ready for next operation */
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/*
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* tSendDelay clocks, avoids signal reflections when switching
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* from receive of response back to send of data.
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*/
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local_irq_save(flags);
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local_irq_save(flags);
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clock_zeros(master, FSI_GPIO_PRIME_SLAVE_CLOCKS);
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clock_zeros(master, FSI_SEND_DELAY_CLOCKS);
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local_irq_restore(flags);
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local_irq_restore(flags);
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return rc;
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return rc;
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