Bitmain SoC changes for v5.1:
- Document Bitmain BM1880 SoC bindings - Add ARCH_BITMAIN for supporting Bitmain SoC platforms - Add devicetree support for Bitmain BM1880 SoC - Add devicetree support for Sophon Edge board - Add MAINTAINERS entry for Bitmain SoC platform -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEZ6VDKoFIy9ikWCeXVZ8R5v6RzvUFAlxes/cACgkQVZ8R5v6R zvXU6wf/cJxHGTZGs/kTpV217G1RzG7LN6YAYyl9707d61Vk9va+0NiV2W32+0w2 EqDARP09SzeFLIjQ275CLzAqqQC4hnnuB0hF4ZwBMXtDGlohaBmfVu3+B8SxqVDE d0Y+wuGtO4MRe5HfClayfvVf3kx6SjQY5C7bJz2RJVf69QCZK2q+a9R21cckMkEb 4EBvgId0FoIIkZJ0CYLN1T4u1i0zpTBfCEmpkInmbdcjMBlZS4+BCwR+KuM6Lwns 7UUF0eBAhFN/A23W9+7VT9CZi3n6ipRSCx0dUXXEUEst0yr3YWhsnWaS88UOGbDD xiKRl8+C7/uO1kUZ9cxQoPWlYRVqlQ== =W7/m -----END PGP SIGNATURE----- Merge tag 'bitmain-initial-soc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/newsoc Bitmain SoC changes for v5.1: - Document Bitmain BM1880 SoC bindings - Add ARCH_BITMAIN for supporting Bitmain SoC platforms - Add devicetree support for Bitmain BM1880 SoC - Add devicetree support for Sophon Edge board - Add MAINTAINERS entry for Bitmain SoC platform * tag 'bitmain-initial-soc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain: MAINTAINERS: Add entry for Bitmain SoC platform arm64: dts: bitmain: Add Sophon Egde board support arm64: dts: bitmain: Add BM1880 SoC support arm64: Add ARCH_BITMAIN platform dt-bindings: arm: Document Bitmain BM1880 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
ee036df9bd
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@ -0,0 +1,18 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/bitmain.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain platform device tree bindings
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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compatible:
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items:
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- enum:
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- bitmain,sophon-edge
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- const: bitmain,bm1880
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...
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@ -1372,6 +1372,13 @@ F: arch/arm/mach-aspeed/
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F: arch/arm/boot/dts/aspeed-*
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N: aspeed
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ARM/BITMAIN ARCHITECTURE
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm64/boot/dts/bitmain/
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F: Documentation/devicetree/bindings/arm/bitmain.yaml
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ARM/CALXEDA HIGHBANK ARCHITECTURE
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M: Rob Herring <robh@kernel.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -52,6 +52,11 @@ config ARCH_BERLIN
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help
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This enables support for Marvell Berlin SoC Family
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config ARCH_BITMAIN
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bool "Bitmain SoC Platforms"
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help
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This enables support for the Bitmain SoC Family.
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config ARCH_BRCMSTB
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bool "Broadcom Set-Top-Box SoCs"
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select BRCMSTB_L2_IRQ
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@ -7,6 +7,7 @@ subdir-y += amd
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subdir-y += amlogic
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subdir-y += apm
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subdir-y += arm
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subdir-y += bitmain
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subdir-y += broadcom
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subdir-y += cavium
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subdir-y += exynos
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0+
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dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb
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@ -0,0 +1,50 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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/dts-v1/;
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#include "bm1880.dtsi"
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/ {
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compatible = "bitmain,sophon-edge", "bitmain,bm1880";
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model = "Sophon Edge";
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aliases {
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serial0 = &uart0;
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serial1 = &uart2;
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serial2 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
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};
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uart_clk: uart-clk {
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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#clock-cells = <0>;
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};
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};
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&uart0 {
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status = "okay";
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clocks = <&uart_clk>;
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};
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&uart1 {
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status = "okay";
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clocks = <&uart_clk>;
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};
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&uart2 {
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status = "okay";
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clocks = <&uart_clk>;
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};
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@ -0,0 +1,119 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "bitmain,bm1880";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secmon@100000000 {
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reg = <0x1 0x00000000 0x0 0x20000>;
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no-map;
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};
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jpu@130000000 {
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reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
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no-map;
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};
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vpu@138000000 {
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reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@50001000 {
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compatible = "arm,gic-400";
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reg = <0x0 0x50001000 0x0 0x1000>,
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<0x0 0x50002000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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uart0: serial@58018000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x58018000 0x0 0x2000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@5801A000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801a000 0x0 0x2000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@5801C000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801c000 0x0 0x2000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@5801E000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801e000 0x0 0x2000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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};
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};
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Loading…
Reference in New Issue