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e1000: M88 PHY workaround

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M88 rev 2 PHY needs a longer downshift to function properly. This adds
a much longer downshift counter for this specific device.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
This commit is contained in:
Auke Kok 2006-06-27 09:08:03 -07:00 committed by Auke Kok
parent f1b3a85354
commit ee04022a21
2 changed files with 41 additions and 18 deletions
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16
drivers/net/e1000/e1000_hw.c
View file

@ -1569,6 +1569,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
if (ret_val) if (ret_val)
return ret_val; return ret_val;
if (hw->phy_revision < M88E1011_I_REV_4) {
/* Force TX_CLK in the Extended PHY Specific Control Register /* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock. * to 25MHz clock.
*/ */
@ -1578,16 +1579,27 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
phy_data |= M88E1000_EPSCR_TX_CLK_25; phy_data |= M88E1000_EPSCR_TX_CLK_25;
if (hw->phy_revision < M88E1011_I_REV_4) { if ((hw->phy_revision == E1000_REVISION_2) &&
(hw->phy_id == M88E1111_I_PHY_ID)) {
/* Vidalia Phy, set the downshift counter to 5x */
phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
ret_val = e1000_write_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
if (ret_val)
return ret_val;
} else {
/* Configure Master and Slave downshift values */ /* Configure Master and Slave downshift values */
phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); ret_val = e1000_write_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
if (ret_val) if (ret_val)
return ret_val; return ret_val;
} }
}
/* SW Reset the PHY so all changes take effect */ /* SW Reset the PHY so all changes take effect */
ret_val = e1000_phy_reset(hw); ret_val = e1000_phy_reset(hw);

11
drivers/net/e1000/e1000_hw.h
View file

@ -2765,6 +2765,17 @@ struct e1000_host_command_info {
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
/* M88EC018 Rev 2 specific DownShift settings */
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
/* IGP01E1000 Specific Port Config Register - R/W */ /* IGP01E1000 Specific Port Config Register - R/W */
#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define IGP01E1000_PSCFR_PRE_EN 0x0020 #define IGP01E1000_PSCFR_PRE_EN 0x0020