e1000: M88 PHY workaround
M88 rev 2 PHY needs a longer downshift to function properly. This adds a much longer downshift counter for this specific device. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
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@ -1565,28 +1565,40 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
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phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
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phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
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if(hw->disable_polarity_correction == 1)
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if(hw->disable_polarity_correction == 1)
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phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
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phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
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ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
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ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
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if(ret_val)
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if (ret_val)
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return ret_val;
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/* Force TX_CLK in the Extended PHY Specific Control Register
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* to 25MHz clock.
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*/
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ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
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if(ret_val)
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return ret_val;
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return ret_val;
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phy_data |= M88E1000_EPSCR_TX_CLK_25;
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if (hw->phy_revision < M88E1011_I_REV_4) {
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if (hw->phy_revision < M88E1011_I_REV_4) {
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/* Configure Master and Slave downshift values */
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/* Force TX_CLK in the Extended PHY Specific Control Register
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phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
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* to 25MHz clock.
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M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
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*/
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phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
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ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
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M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
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if (ret_val)
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ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
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if(ret_val)
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return ret_val;
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return ret_val;
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phy_data |= M88E1000_EPSCR_TX_CLK_25;
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if ((hw->phy_revision == E1000_REVISION_2) &&
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(hw->phy_id == M88E1111_I_PHY_ID)) {
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/* Vidalia Phy, set the downshift counter to 5x */
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phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
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phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
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ret_val = e1000_write_phy_reg(hw,
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M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
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if (ret_val)
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return ret_val;
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} else {
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/* Configure Master and Slave downshift values */
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phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
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M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
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phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
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M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
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ret_val = e1000_write_phy_reg(hw,
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M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
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if (ret_val)
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return ret_val;
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}
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}
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}
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/* SW Reset the PHY so all changes take effect */
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/* SW Reset the PHY so all changes take effect */
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@ -2765,6 +2765,17 @@ struct e1000_host_command_info {
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#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
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#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
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#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
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#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
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/* M88EC018 Rev 2 specific DownShift settings */
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
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#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
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/* IGP01E1000 Specific Port Config Register - R/W */
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/* IGP01E1000 Specific Port Config Register - R/W */
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#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
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#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
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#define IGP01E1000_PSCFR_PRE_EN 0x0020
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#define IGP01E1000_PSCFR_PRE_EN 0x0020
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