drm/i915: Replace WARN inside I915_READ64_2x32 with retry loop
Since we may conceivably encounter situations where the upper part of the 64bit register changes between reads, for example when a timestamp counter overflows, change the WARN into a retry loop. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3303,15 +3303,14 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
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#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
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#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
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#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
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#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
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u32 upper = I915_READ(upper_reg); \
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u32 upper, lower, tmp; \
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u32 lower = I915_READ(lower_reg); \
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tmp = I915_READ(upper_reg); \
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u32 tmp = I915_READ(upper_reg); \
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do { \
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if (upper != tmp) { \
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upper = tmp; \
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upper = tmp; \
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lower = I915_READ(lower_reg); \
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lower = I915_READ(lower_reg); \
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tmp = I915_READ(upper_reg); \
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WARN_ON(I915_READ(upper_reg) != upper); \
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} while (upper != tmp); \
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} \
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(u64)upper << 32 | lower; })
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(u64)upper << 32 | lower; })
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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