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ARM: dts: at91: sama5d3: fix maximum peripheral clock rates 

Currently the maximum rate for peripheral clock is calculated based on a
typical 133MHz MCK. The maximum frequency is defined in the datasheet as a
ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the
device trees to match the maximum rate based on 166MHz.

Reported-by: Karl Rudbæk Olsen <karl@micro-technic.com>
Fixes: d2e8190b79 ("ARM: at91/dt: define sama5d3 clocks")
Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
alistair/sensors
Alexandre Belloni 2020-01-10 18:20:06 +01:00
parent 0a79e952a8
commit ee0aa926dd
3 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -1188,49 +1188,49 @@
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <12>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <13>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <14>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <15>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <16>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
twi0_clk: twi0_clk {
reg = <18>;
#clock-cells = <0>;
atmel,clk-output-range = <0 16625000>;
atmel,clk-output-range = <0 41500000>;
};
twi1_clk: twi1_clk {
#clock-cells = <0>;
reg = <19>;
atmel,clk-output-range = <0 16625000>;
atmel,clk-output-range = <0 41500000>;
};
twi2_clk: twi2_clk {
#clock-cells = <0>;
reg = <20>;
atmel,clk-output-range = <0 16625000>;
atmel,clk-output-range = <0 41500000>;
};
mci0_clk: mci0_clk {
@ -1246,19 +1246,19 @@
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <24>;
atmel,clk-output-range = <0 133000000>;
atmel,clk-output-range = <0 166000000>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <25>;
atmel,clk-output-range = <0 133000000>;
atmel,clk-output-range = <0 166000000>;
};
tcb0_clk: tcb0_clk {
#clock-cells = <0>;
reg = <26>;
atmel,clk-output-range = <0 133000000>;
atmel,clk-output-range = <0 166000000>;
};
pwm_clk: pwm_clk {
@ -1269,7 +1269,7 @@
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <29>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
dma0_clk: dma0_clk {
@ -1300,13 +1300,13 @@
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <38>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
ssc1_clk: ssc1_clk {
#clock-cells = <0>;
reg = <39>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
sha_clk: sha_clk {

4
arch/arm/boot/dts/sama5d3_can.dtsi
View File

@ -36,13 +36,13 @@
can0_clk: can0_clk {
#clock-cells = <0>;
reg = <40>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
can1_clk: can1_clk {
#clock-cells = <0>;
reg = <41>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
};
};

4
arch/arm/boot/dts/sama5d3_uart.dtsi
View File

@ -41,13 +41,13 @@
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <16>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <17>;
atmel,clk-output-range = <0 66000000>;
atmel,clk-output-range = <0 83000000>;
};
};
};