ARM: imx6: clk: i.MX6 DualLite/Solo i2c4 clock
Compared to i.MX6 Quad/Dual the CCM_CCGR1 register in the i.MX6 Solo/DualLite replaces the ecspi5 clock with the i2c4 clock. Handle this difference using cpu_is_imx6dl(). Signed-off-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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@ -352,7 +352,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
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clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
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clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
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clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
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if (cpu_is_imx6dl())
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/* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
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clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
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else
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clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
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clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
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clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
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clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
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