drm/i915: consider the source max DP lane count too
Even if the panel claims it can support 4 lanes, there's the possibility that the HW can't, so consider this while selecting the max lane count. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -121,6 +121,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
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return max_link_bw;
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}
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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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u8 source_max, sink_max;
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source_max = 4;
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if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
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(intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
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source_max = 2;
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sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
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return min(source_max, sink_max);
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}
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/*
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* The units on the numbers in the next two are... bizarre. Examples will
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* make it clearer; this one parallels an example in the eDP spec.
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@ -171,7 +187,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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}
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max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
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max_lanes = intel_dp_max_lane_count(intel_dp);
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max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
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mode_rate = intel_dp_link_required(target_clock, 18);
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@ -751,7 +767,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc *intel_crtc = encoder->new_crtc;
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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int lane_count, clock;
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int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
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int max_lane_count = intel_dp_max_lane_count(intel_dp);
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/* Conveniently, the link BW constants become indices with a shift...*/
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int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
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int bpp, mode_rate;
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