drm/i915/bxt: add description about the BXT PHYs
Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics. v2: - add more detail about the mapping between ports and transcoders (ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
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<title>DPIO</title>
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!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
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<table id="dpiox2">
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<title>Dual channel PHY (VLV/CHV)</title>
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<title>Dual channel PHY (VLV/CHV/BXT)</title>
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<tgroup cols="8">
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<colspec colname="c0" />
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<colspec colname="c1" />
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@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
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</tgroup>
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</table>
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<table id="dpiox1">
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<title>Single channel PHY (CHV)</title>
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<title>Single channel PHY (CHV/BXT)</title>
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<tgroup cols="4">
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<colspec colname="c0" />
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<colspec colname="c1" />
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@ -715,7 +715,7 @@ enum skl_disp_power_wells {
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/**
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* DOC: DPIO
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*
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* VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
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* VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
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* ports. DPIO is the name given to such a display PHY. These PHYs
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* don't follow the standard programming model using direct MMIO
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* registers, and instead their registers must be accessed trough IOSF
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@ -746,7 +746,7 @@ enum skl_disp_power_wells {
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* controlled from the display controller side. No DPIO registers
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* need to be accessed during AUX communication,
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*
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* Generally the common lane corresponds to the pipe and
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* Generally on VLV/CHV the common lane corresponds to the pipe and
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* the spline (PCS/TX) corresponds to the port.
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*
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* For dual channel PHY (VLV/CHV):
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@ -768,11 +768,17 @@ enum skl_disp_power_wells {
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*
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* port D == PCS/TX CH0
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*
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* Note: digital port B is DDI0, digital port C is DDI1,
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* digital port D is DDI2
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* On BXT the entire PHY channel corresponds to the port. That means
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* the PLL is also now associated with the port rather than the pipe,
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* and so the clock needs to be routed to the appropriate transcoder.
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* Port A PLL is directly connected to transcoder EDP and port B/C
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* PLLs can be routed to any transcoder A/B/C.
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*
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* Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
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* digital port D (CHV) or port A (BXT).
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*/
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/*
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* Dual channel PHY (VLV/CHV)
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* Dual channel PHY (VLV/CHV/BXT)
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* ---------------------------------
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* | CH0 | CH1 |
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* | CMN/PLL/REF | CMN/PLL/REF |
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@ -784,7 +790,7 @@ enum skl_disp_power_wells {
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* | DDI0 | DDI1 | DP/HDMI ports
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* ---------------------------------
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*
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* Single channel PHY (CHV)
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* Single channel PHY (CHV/BXT)
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* -----------------
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* | CH0 |
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* | CMN/PLL/REF |
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