ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>hifive-unleashed-5.1
Uwe Kleine-König
parent
6d85e2b0b6
commit
ef43eff344
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@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
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dove-d2plug.dtb \
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dove-d3plug.dtb \
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dove-dove-db.dtb
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dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
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dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
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exynos4210-smdkv310.dtb \
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exynos4210-trats.dtb \
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@ -0,0 +1,18 @@
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#include "skeleton.dtsi"
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/ {
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nvic: nv-interrupt-controller {
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compatible = "arm,armv7m-nvic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xe000e100 0xc00>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&nvic>;
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ranges;
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};
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};
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@ -0,0 +1,86 @@
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/*
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* Device tree for EFM32GG-DK3750 development board.
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*
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* Documentation available from
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* http://www.silabs.com/Support%20Documents/TechnicalDocs/efm32gg-dk3750-ug.pdf
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*/
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/dts-v1/;
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#include "efm32gg.dtsi"
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/ {
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model = "Energy Micro Giant Gecko Development Kit";
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compatible = "efm32,dk3750";
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chosen {
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bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0";
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};
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memory {
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reg = <0x88000000 0x400000>;
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};
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soc {
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adc@40002000 {
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status = "ok";
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};
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i2c@4000a000 {
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location = <3>;
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status = "ok";
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temp@48 {
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compatible = "st,stds75";
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reg = <0x48>;
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};
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eeprom@50 {
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compatible = "microchip,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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spi0: spi@4000c000 { /* USART0 */
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cs-gpios = <&gpio 68 1>; // E4
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location = <1>;
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status = "ok";
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microsd@0 {
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compatible = "mmc-spi-slot";
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spi-max-frequency = <100000>;
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voltage-ranges = <3200 3400>;
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broken-cd;
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reg = <0>;
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};
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};
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spi1: spi@4000c400 { /* USART1 */
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cs-gpios = <&gpio 51 1>; // D3
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location = <1>;
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status = "ok";
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ks8851@0 {
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compatible = "ks8851";
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spi-max-frequency = <6000000>;
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reg = <0>;
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interrupt-parent = <&boardfpga>;
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interrupts = <4>;
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};
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};
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uart4: uart@4000e400 { /* UART1 */
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location = <2>;
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status = "ok";
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};
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boardfpga: boardfpga {
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compatible = "efm32board";
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reg = <0x80000000 0x400>;
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irq-gpios = <&gpio 64 1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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status = "ok";
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};
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};
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};
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@ -0,0 +1,172 @@
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/*
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* Device tree for Energy Micro EFM32 Giant Gecko SoC.
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*
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* Documentation available from
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* http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf
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*/
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#include "armv7-m.dtsi"
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#include "dt-bindings/clock/efm32-cmu.h"
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/ {
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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};
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soc {
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adc: adc@40002000 {
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compatible = "efm32,adc";
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reg = <0x40002000 0x400>;
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interrupts = <7>;
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clocks = <&cmu clk_HFPERCLKADC0>;
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status = "disabled";
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};
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gpio: gpio@40006000 {
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compatible = "efm32,gpio";
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reg = <0x40006000 0x1000>;
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interrupts = <1 11>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&cmu clk_HFPERCLKGPIO>;
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status = "ok";
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};
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i2c0: i2c@4000a000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "efm32,i2c";
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reg = <0x4000a000 0x400>;
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interrupts = <9>;
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clocks = <&cmu clk_HFPERCLKI2C0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@4000a400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "efm32,i2c";
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reg = <0x4000a400 0x400>;
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interrupts = <10>;
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clocks = <&cmu clk_HFPERCLKI2C1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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spi0: spi@4000c000 { /* USART0 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "efm32,spi";
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reg = <0x4000c000 0x400>;
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interrupts = <3 4>;
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clocks = <&cmu clk_HFPERCLKUSART0>;
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status = "disabled";
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};
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spi1: spi@4000c400 { /* USART1 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "efm32,spi";
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reg = <0x4000c400 0x400>;
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interrupts = <15 16>;
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clocks = <&cmu clk_HFPERCLKUSART1>;
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status = "disabled";
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};
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spi2: spi@40x4000c800 { /* USART2 */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "efm32,spi";
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reg = <0x4000c800 0x400>;
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interrupts = <18 19>;
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clocks = <&cmu clk_HFPERCLKUSART2>;
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status = "disabled";
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};
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uart0: uart@4000c000 { /* USART0 */
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compatible = "efm32,uart";
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reg = <0x4000c000 0x400>;
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interrupts = <3 4>;
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clocks = <&cmu clk_HFPERCLKUSART0>;
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status = "disabled";
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};
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uart1: uart@4000c400 { /* USART1 */
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compatible = "efm32,uart";
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reg = <0x4000c400 0x400>;
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interrupts = <15 16>;
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clocks = <&cmu clk_HFPERCLKUSART1>;
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status = "disabled";
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};
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uart2: uart@40x4000c800 { /* USART2 */
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compatible = "efm32,uart";
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reg = <0x4000c800 0x400>;
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interrupts = <18 19>;
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clocks = <&cmu clk_HFPERCLKUSART2>;
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status = "disabled";
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};
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uart3: uart@4000e000 { /* UART0 */
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compatible = "efm32,uart";
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reg = <0x4000e000 0x400>;
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interrupts = <20 21>;
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clocks = <&cmu clk_HFPERCLKUART0>;
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status = "disabled";
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};
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uart4: uart@4000e400 { /* UART1 */
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compatible = "efm32,uart";
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reg = <0x4000e400 0x400>;
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interrupts = <22 23>;
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clocks = <&cmu clk_HFPERCLKUART1>;
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status = "disabled";
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};
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timer0: timer@40010000 {
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compatible = "efm32,timer";
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reg = <0x40010000 0x400>;
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interrupts = <2>;
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clocks = <&cmu clk_HFPERCLKTIMER0>;
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};
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timer1: timer@40010400 {
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compatible = "efm32,timer";
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reg = <0x40010400 0x400>;
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interrupts = <12>;
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clocks = <&cmu clk_HFPERCLKTIMER1>;
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};
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timer2: timer@40010800 {
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compatible = "efm32,timer";
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reg = <0x40010800 0x400>;
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interrupts = <13>;
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clocks = <&cmu clk_HFPERCLKTIMER2>;
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};
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timer3: timer@40010c00 {
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compatible = "efm32,timer";
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reg = <0x40010c00 0x400>;
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interrupts = <14>;
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clocks = <&cmu clk_HFPERCLKTIMER3>;
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};
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cmu: cmu@400c8000 {
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compatible = "efm32gg,cmu";
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reg = <0x400c8000 0x400>;
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interrupts = <32>;
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#clock-cells = <1>;
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};
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};
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};
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