drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable
bit.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200611093015.11370-1-chris@chris-wilson.co.uk
(cherry picked from commit f93ec5fb56
)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
parent
898e4e57ad
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@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
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wa_write_masked_or(wal, reg, set, set);
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}
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static void
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wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
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{
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wa_write_masked_or(wal, reg, clr, 0);
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}
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static void
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wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
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{
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@ -686,6 +692,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
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return 0;
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}
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static void
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hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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/* L3 caching of data atomics doesn't work -- disable it. */
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wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
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wa_add(wal,
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HSW_ROW_CHICKEN3, 0,
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_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
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0 /* XXX does this reg exist? */);
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/* WaVSRefCountFullforceMissDisable:hsw */
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wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
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wa_masked_dis(wal,
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CACHE_MODE_0_GEN7,
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/* WaDisable_RenderCache_OperationalFlush:hsw */
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RC_OP_FLUSH_ENABLE |
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/* enable HiZ Raw Stall Optimization */
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HIZ_RAW_STALL_OPT_DISABLE);
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/* WaDisable4x2SubspanOptimization:hsw */
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wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal, GEN7_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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/* WaSampleCChickenBitEnable:hsw */
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wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
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}
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static void
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gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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@ -963,6 +1009,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
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bxt_gt_workarounds_init(i915, wal);
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else if (IS_SKYLAKE(i915))
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skl_gt_workarounds_init(i915, wal);
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else if (IS_HASWELL(i915))
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hsw_gt_workarounds_init(i915, wal);
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else if (INTEL_GEN(i915) <= 8)
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return;
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else
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@ -7230,45 +7230,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
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static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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/* L3 caching of data atomics doesn't work -- disable it. */
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I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
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I915_WRITE(HSW_ROW_CHICKEN3,
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_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
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/* This is required by WaCatErrorRejectionIssue:hsw */
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I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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/* WaVSRefCountFullforceMissDisable:hsw */
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I915_WRITE(GEN7_FF_THREAD_MODE,
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I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
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/* WaDisable_RenderCache_OperationalFlush:hsw */
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I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
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/* enable HiZ Raw Stall Optimization */
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I915_WRITE(CACHE_MODE_0_GEN7,
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_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
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/* WaDisable4x2SubspanOptimization:hsw */
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I915_WRITE(CACHE_MODE_1,
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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I915_WRITE(GEN7_GT_MODE,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
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/* WaSampleCChickenBitEnable:hsw */
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I915_WRITE(HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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/* WaSwitchSolVfFArbitrationPriority:hsw */
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I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
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