drm/i915/chv: find the best divisor for the target clock v4
Based on the chv clock limit, find the best divisor. The divisor data has been verified with this spreadsheet. P1273_DPLL_Programming Spreadsheet. v2: Rebase the code and change the chv_find_best_dpll based on new standard way to use intel_PLL_is_valid. Besides, clean up some extra variables. v3: Ville suggest better fixed point for m2 calculation. v4: -Add comment for the limit is compute using fast clock. (Ville) -Don't pass the request clock to chv_clock, as the same function will be use clock readout, which doens't have request clock. (Ville) -Add and use DIV_ROUND_CLOSEST_ULL to consistent with other clock calculation. (Ville) -Fix the dp m2 after m2 has stored fixed point. (Ville) Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> [vsyrjala: Avoid div-by-zero in chv_clock()] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -41,6 +41,9 @@
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#include <drm/drm_crtc_helper.h>
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#include <linux/dma_remapping.h>
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#define DIV_ROUND_CLOSEST_ULL(ll, d) \
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({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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@ -328,6 +331,22 @@ static const intel_limit_t intel_limits_vlv = {
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.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
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};
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static const intel_limit_t intel_limits_chv = {
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/*
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* These are the data rate limits (measured in fast clocks)
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* since those are the strictest limits we have. The fast
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* clock and actual rate limits are more relaxed, so checking
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* them would make no difference.
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*/
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.dot = { .min = 25000 * 5, .max = 540000 * 5},
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.vco = { .min = 4860000, .max = 6700000 },
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.n = { .min = 1, .max = 1 },
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.m1 = { .min = 2, .max = 2 },
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.m2 = { .min = 24 << 22, .max = 175 << 22 },
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.p1 = { .min = 2, .max = 4 },
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.p2 = { .p2_slow = 1, .p2_fast = 14 },
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};
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static void vlv_clock(int refclk, intel_clock_t *clock)
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{
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clock->m = clock->m1 * clock->m2;
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@ -412,6 +431,8 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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limit = &intel_limits_pineview_lvds;
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else
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limit = &intel_limits_pineview_sdvo;
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} else if (IS_CHERRYVIEW(dev)) {
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limit = &intel_limits_chv;
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} else if (IS_VALLEYVIEW(dev)) {
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limit = &intel_limits_vlv;
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} else if (!IS_GEN2(dev)) {
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@ -456,6 +477,17 @@ static void i9xx_clock(int refclk, intel_clock_t *clock)
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clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
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}
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static void chv_clock(int refclk, intel_clock_t *clock)
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{
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clock->m = clock->m1 * clock->m2;
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clock->p = clock->p1 * clock->p2;
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if (WARN_ON(clock->n == 0 || clock->p == 0))
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return;
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clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
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clock->n << 22);
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clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
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}
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#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
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/**
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* Returns whether the given set of divisors are valid for a given refclk with
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@ -731,6 +763,58 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
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return found;
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}
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static bool
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chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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intel_clock_t clock;
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uint64_t m2;
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int found = false;
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memset(best_clock, 0, sizeof(*best_clock));
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/*
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* Based on hardware doc, the n always set to 1, and m1 always
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* set to 2. If requires to support 200Mhz refclk, we need to
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* revisit this because n may not 1 anymore.
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*/
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clock.n = 1, clock.m1 = 2;
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target *= 5; /* fast clock */
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for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
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for (clock.p2 = limit->p2.p2_fast;
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clock.p2 >= limit->p2.p2_slow;
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clock.p2 -= clock.p2 > 10 ? 2 : 1) {
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clock.p = clock.p1 * clock.p2;
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m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
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clock.n) << 22, refclk * clock.m1);
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if (m2 > INT_MAX/clock.m1)
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continue;
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clock.m2 = m2;
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chv_clock(refclk, &clock);
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if (!intel_PLL_is_valid(dev, limit, &clock))
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continue;
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/* based on hardware requirement, prefer bigger p
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*/
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if (clock.p > best_clock->p) {
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*best_clock = clock;
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found = true;
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}
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}
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}
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return found;
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}
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bool intel_crtc_active(struct drm_crtc *crtc)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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@ -11004,6 +11088,8 @@ static void intel_init_display(struct drm_device *dev)
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if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
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dev_priv->display.find_dpll = g4x_find_best_dpll;
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else if (IS_CHERRYVIEW(dev))
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dev_priv->display.find_dpll = chv_find_best_dpll;
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else if (IS_VALLEYVIEW(dev))
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dev_priv->display.find_dpll = vlv_find_best_dpll;
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else if (IS_PINEVIEW(dev))
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@ -64,6 +64,24 @@ static const struct dp_link_dpll vlv_dpll[] = {
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{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
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};
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/*
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* CHV supports eDP 1.4 that have more link rates.
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* Below only provides the fixed rate but exclude variable rate.
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*/
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static const struct dp_link_dpll chv_dpll[] = {
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/*
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* CHV requires to program fractional division for m2.
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* m2 is stored in fixed point format using formula below
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* (m2_int << 22) | m2_fraction
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*/
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{ DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
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{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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{ DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
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{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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{ DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
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{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
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};
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/**
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* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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* @intel_dp: DP struct
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@ -726,6 +744,9 @@ intel_dp_set_clock(struct intel_encoder *encoder,
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} else if (HAS_PCH_SPLIT(dev)) {
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divisor = pch_dpll;
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count = ARRAY_SIZE(pch_dpll);
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} else if (IS_CHERRYVIEW(dev)) {
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divisor = chv_dpll;
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count = ARRAY_SIZE(chv_dpll);
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} else if (IS_VALLEYVIEW(dev)) {
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divisor = vlv_dpll;
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count = ARRAY_SIZE(vlv_dpll);
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