staging: media: imx: enable ISI for imx8mn platform
ISI is image sensor interface of imx8 family. It's reused in imx8mn platform. But they use different clock tree, so driver need to select the related clock operation for different platform. In order to solve the problem, driver define mxc_isi_dev_ops which used to control clock operation. Dispmix subsystem of imx8mn is consist of ISI, CSI, DSI and LCDIF modules. It use GPR to manage the reset and clock signal for all modules. We add a reset driver for dispmix reset function, so add related consumer of reset in ISI core driver. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>5.4-rM2-2.2.x-imx-squashed
Guoniu.zhou
parent
d8977ba09f
commit
f093fe3262
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@ -166,7 +166,8 @@ struct mxc_isi_fmt *mxc_isi_get_src_fmt(struct v4l2_subdev_format *sd_fmt)
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if (sd_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16 ||
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sd_fmt->format.code == MEDIA_BUS_FMT_YVYU8_2X8 ||
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sd_fmt->format.code == MEDIA_BUS_FMT_AYUV8_1X32 ||
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sd_fmt->format.code == MEDIA_BUS_FMT_UYVY8_2X8)
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sd_fmt->format.code == MEDIA_BUS_FMT_UYVY8_2X8 ||
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sd_fmt->format.code == MEDIA_BUS_FMT_YUYV8_2X8)
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index = 1;
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else
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index = 0;
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@ -1134,6 +1135,7 @@ static int mxc_isi_cap_enum_framesizes(struct file *file, void *priv,
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struct v4l2_frmsizeenum *fsize)
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{
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struct mxc_isi_cap_dev *isi_cap = video_drvdata(file);
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struct device_node *parent;
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struct v4l2_subdev *sd;
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struct mxc_isi_fmt *fmt;
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struct v4l2_subdev_frame_size_enum fse = {
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@ -1157,6 +1159,11 @@ static int mxc_isi_cap_enum_framesizes(struct file *file, void *priv,
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if (ret)
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return ret;
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parent = of_get_parent(isi_cap->pdev->dev.of_node);
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if ((of_device_is_compatible(parent, "fsl,imx8mn-isi")) &&
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(fse.max_width > ISI_2K || fse.min_width > ISI_2K))
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return -EINVAL;
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if (fse.min_width == fse.max_width &&
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fse.min_height == fse.max_height) {
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fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
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@ -1180,6 +1187,7 @@ static int mxc_isi_cap_enum_frameintervals(struct file *file, void *fh,
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struct v4l2_frmivalenum *interval)
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{
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struct mxc_isi_cap_dev *isi_cap = video_drvdata(file);
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struct device_node *parent;
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struct v4l2_subdev *sd;
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struct mxc_isi_fmt *fmt;
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struct v4l2_subdev_frame_interval_enum fie = {
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@ -1203,6 +1211,11 @@ static int mxc_isi_cap_enum_frameintervals(struct file *file, void *fh,
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if (ret)
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return ret;
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parent = of_get_parent(isi_cap->pdev->dev.of_node);
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if (of_device_is_compatible(parent, "fsl,imx8mn-isi") &&
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fie.width > ISI_2K)
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return -EINVAL;
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interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
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interval->discrete = fie.interval;
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@ -1353,6 +1366,7 @@ static int mxc_isi_subdev_set_fmt(struct v4l2_subdev *sd,
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struct v4l2_subdev_format *fmt)
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{
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struct mxc_isi_cap_dev *isi_cap = v4l2_get_subdevdata(sd);
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struct device_node *parent;
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struct v4l2_mbus_framefmt *mf = &fmt->format;
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struct mxc_isi_frame *dst_f = &isi_cap->dst_f;
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struct mxc_isi_fmt *out_fmt;
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@ -1373,6 +1387,11 @@ static int mxc_isi_subdev_set_fmt(struct v4l2_subdev *sd,
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return -EINVAL;
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}
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parent = of_get_parent(isi_cap->pdev->dev.of_node);
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if (of_device_is_compatible(parent, "fsl,imx8mn-isi") &&
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mf->width > ISI_2K)
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return -EINVAL;
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mutex_lock(&isi_cap->lock);
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/* update out put frame size and formate */
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dst_f->fmt = &mxc_isi_out_formats[i];
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@ -6,6 +6,8 @@
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#include "imx8-isi-hw.h"
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static const struct of_device_id mxc_isi_of_match[];
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struct mxc_isi_dev *mxc_isi_get_hostdata(struct platform_device *pdev)
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{
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struct mxc_isi_dev *mxc_isi;
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@ -55,6 +57,7 @@ static irqreturn_t mxc_isi_irq_handler(int irq, void *priv)
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spin_lock(&mxc_isi->slock);
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status = mxc_isi_get_irq_status(mxc_isi);
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mxc_isi->status = status;
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mxc_isi_clean_irq_status(mxc_isi, status);
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if (status & CHNL_STS_FRM_STRD_MASK) {
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@ -88,6 +91,146 @@ static irqreturn_t mxc_isi_irq_handler(int irq, void *priv)
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return IRQ_HANDLED;
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}
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static int disp_mix_sft_rstn(struct reset_control *reset, bool enable)
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{
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int ret;
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if (!reset)
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return 0;
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ret = enable ? reset_control_assert(reset) :
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reset_control_deassert(reset);
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return ret;
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}
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static int disp_mix_clks_enable(struct reset_control *reset, bool enable)
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{
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int ret;
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if (!reset)
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return 0;
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ret = enable ? reset_control_assert(reset) :
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reset_control_deassert(reset);
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return ret;
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}
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static int mxc_imx8_clk_get(struct mxc_isi_dev *mxc_isi)
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{
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struct device *dev = &mxc_isi->pdev->dev;
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mxc_isi->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(mxc_isi->clk)) {
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dev_err(dev, "failed to get isi clk\n");
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return PTR_ERR(mxc_isi->clk);
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}
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return 0;
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}
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static int mxc_imx8_clk_enable(struct mxc_isi_dev *mxc_isi)
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{
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struct device *dev = &mxc_isi->pdev->dev;
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int ret;
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ret = clk_prepare_enable(mxc_isi->clk);
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if (ret < 0) {
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dev_err(dev, "%s, enable clk error\n", __func__);
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return ret;
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}
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return 0;
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}
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static void mxc_imx8_clk_disable(struct mxc_isi_dev *mxc_isi)
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{
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clk_disable_unprepare(mxc_isi->clk);
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}
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static struct mxc_isi_dev_ops mxc_imx8_data = {
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.clk_get = mxc_imx8_clk_get,
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.clk_enable = mxc_imx8_clk_enable,
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.clk_disable = mxc_imx8_clk_disable,
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};
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static int mxc_imx8mn_clk_get(struct mxc_isi_dev *mxc_isi)
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{
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struct device *dev = &mxc_isi->pdev->dev;
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mxc_isi->clk_disp_axi = devm_clk_get(dev, "disp_axi");
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if (IS_ERR(mxc_isi->clk_disp_axi)) {
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dev_err(dev, "failed to get disp_axi clk\n");
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return PTR_ERR(mxc_isi->clk_disp_axi);
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}
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mxc_isi->clk_disp_apb = devm_clk_get(dev, "disp_apb");
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if (IS_ERR(mxc_isi->clk_disp_apb)) {
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dev_err(dev, "failed to get disp_apb clk\n");
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return PTR_ERR(mxc_isi->clk_disp_apb);
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}
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mxc_isi->clk_root_disp_axi = devm_clk_get(dev, "disp_axi_root");
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if (IS_ERR(mxc_isi->clk_root_disp_axi)) {
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dev_err(dev, "failed to get disp axi root clk\n");
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return PTR_ERR(mxc_isi->clk_root_disp_axi);
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}
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mxc_isi->clk_root_disp_apb = devm_clk_get(dev, "disp_apb_root");
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if (IS_ERR(mxc_isi->clk_root_disp_apb)) {
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dev_err(dev, "failed to get disp apb root clk\n");
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return PTR_ERR(mxc_isi->clk_root_disp_apb);
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}
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return 0;
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}
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static int mxc_imx8mn_clk_enable(struct mxc_isi_dev *mxc_isi)
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{
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struct device *dev = &mxc_isi->pdev->dev;
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int ret;
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ret = clk_prepare_enable(mxc_isi->clk_disp_axi);
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if (ret < 0) {
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dev_err(dev, "prepare and enable axi clk error\n");
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return ret;
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}
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ret = clk_prepare_enable(mxc_isi->clk_disp_apb);
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if (ret < 0) {
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dev_err(dev, "prepare and enable abp clk error\n");
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return ret;
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}
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ret = clk_prepare_enable(mxc_isi->clk_root_disp_axi);
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if (ret < 0) {
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dev_err(dev, "prepare and enable axi root clk error\n");
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return ret;
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}
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ret = clk_prepare_enable(mxc_isi->clk_root_disp_apb);
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if (ret < 0) {
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dev_err(dev, "prepare and enable apb root clk error\n");
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return ret;
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}
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return 0;
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}
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static void mxc_imx8mn_clk_disable(struct mxc_isi_dev *mxc_isi)
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{
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clk_disable_unprepare(mxc_isi->clk_root_disp_axi);
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clk_disable_unprepare(mxc_isi->clk_root_disp_apb);
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clk_disable_unprepare(mxc_isi->clk_disp_axi);
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clk_disable_unprepare(mxc_isi->clk_disp_apb);
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}
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static struct mxc_isi_dev_ops mxc_imx8mn_data = {
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.clk_get = mxc_imx8mn_clk_get,
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.clk_enable = mxc_imx8mn_clk_enable,
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.clk_disable = mxc_imx8mn_clk_disable,
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};
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static int mxc_isi_parse_dt(struct mxc_isi_dev *mxc_isi)
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{
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struct device *dev = &mxc_isi->pdev->dev;
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@ -109,25 +252,114 @@ static int mxc_isi_parse_dt(struct mxc_isi_dev *mxc_isi)
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return 0;
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}
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static int mxc_isi_clk_get(struct mxc_isi_dev *mxc_isi)
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{
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const struct mxc_isi_dev_ops *ops = mxc_isi->ops;
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if (!ops && !ops->clk_get)
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return -EINVAL;
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return ops->clk_get(mxc_isi);
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}
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static int mxc_isi_clk_enable(struct mxc_isi_dev *mxc_isi)
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{
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const struct mxc_isi_dev_ops *ops = mxc_isi->ops;
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if (!ops && !ops->clk_enable)
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return -EINVAL;
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return ops->clk_enable(mxc_isi);
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}
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static void mxc_isi_clk_disable(struct mxc_isi_dev *mxc_isi)
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{
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const struct mxc_isi_dev_ops *ops = mxc_isi->ops;
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if (!ops && !ops->clk_disable)
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return;
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ops->clk_disable(mxc_isi);
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}
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static int mxc_isi_of_parse_resets(struct mxc_isi_dev *mxc_isi)
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{
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int ret;
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struct device *dev = &mxc_isi->pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *parent, *child;
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struct of_phandle_args args;
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struct reset_control *rstc;
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const char *compat;
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uint32_t len, rstc_num = 0;
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ret = of_parse_phandle_with_args(np, "resets", "#reset-cells",
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0, &args);
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if (ret)
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return ret;
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parent = args.np;
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for_each_child_of_node(parent, child) {
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compat = of_get_property(child, "compatible", NULL);
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if (!compat)
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continue;
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rstc = of_reset_control_array_get(child, false, false, true);
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if (IS_ERR(rstc))
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continue;
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len = strlen(compat);
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if (!of_compat_cmp("isi,soft-resetn", compat, len)) {
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mxc_isi->soft_resetn = rstc;
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rstc_num++;
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} else if (!of_compat_cmp("isi,clk-enable", compat, len)) {
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mxc_isi->clk_enable = rstc;
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rstc_num++;
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} else {
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dev_warn(dev, "invalid isi reset node: %s\n", compat);
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}
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}
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if (!rstc_num) {
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dev_err(dev, "no invalid reset control exists\n");
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return -EINVAL;
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}
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of_node_put(parent);
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return 0;
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}
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static int mxc_isi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mxc_isi_dev *mxc_isi;
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struct resource *res;
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const struct of_device_id *of_id;
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int ret = 0;
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mxc_isi = devm_kzalloc(dev, sizeof(*mxc_isi), GFP_KERNEL);
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if (!mxc_isi)
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return -ENOMEM;
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mxc_isi->pdev = pdev;
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of_id = of_match_node(mxc_isi_of_match, dev->of_node);
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if (!of_id)
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return -EINVAL;
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mxc_isi->ops = of_id->data;
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if (!mxc_isi->ops) {
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dev_err(dev, "Can't get platform device data\n");
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return -EINVAL;
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}
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ret = mxc_isi_parse_dt(mxc_isi);
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if (ret < 0)
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return ret;
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if (mxc_isi->id >= MXC_ISI_MAX_DEVS || mxc_isi->id < 0) {
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dev_err(dev, "Invalid driver data or device id (%d)\n", mxc_isi->id);
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dev_err(dev, "Invalid driver data or device id (%d)\n",
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mxc_isi->id);
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return -EINVAL;
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}
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@ -135,16 +367,18 @@ static int mxc_isi_probe(struct platform_device *pdev)
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mutex_init(&mxc_isi->lock);
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atomic_set(&mxc_isi->usage_count, 0);
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mxc_isi->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(mxc_isi->clk)) {
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dev_err(dev, "failed to get isi clk\n");
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return PTR_ERR(mxc_isi->clk);
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if (of_device_is_compatible(dev->of_node, "fsl,imx8mn-isi")) {
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ret = mxc_isi_of_parse_resets(mxc_isi);
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if (ret) {
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dev_warn(dev, "Can not parse reset control\n");
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return ret;
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}
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}
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ret = clk_prepare_enable(mxc_isi->clk);
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ret = mxc_isi_clk_get(mxc_isi);
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if (ret < 0) {
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dev_err(dev, "Prepare and enable isi clk error (%d)\n", ret);
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return -EINVAL;
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dev_err(dev, "ISI_%d get clocks fail\n", mxc_isi->id);
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return ret;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -154,18 +388,26 @@ static int mxc_isi_probe(struct platform_device *pdev)
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return PTR_ERR(mxc_isi->regs);
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}
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ret = mxc_isi_clk_enable(mxc_isi);
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if (ret < 0) {
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dev_err(dev, "ISI_%d enable clocks fail\n", mxc_isi->id);
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return ret;
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}
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disp_mix_sft_rstn(mxc_isi->soft_resetn, false);
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disp_mix_clks_enable(mxc_isi->clk_enable, true);
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mxc_isi_clean_registers(mxc_isi);
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res) {
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dev_err(dev, "Failed to get IRQ resource\n");
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return -ENXIO;
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goto err;
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}
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ret = devm_request_irq(dev, res->start, mxc_isi_irq_handler,
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0, dev_name(dev), mxc_isi);
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if (ret < 0) {
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dev_err(dev, "failed to install irq (%d)\n", ret);
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return -EINVAL;
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goto err;
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}
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mxc_isi_channel_set_chain_buf(mxc_isi);
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@ -174,13 +416,19 @@ static int mxc_isi_probe(struct platform_device *pdev)
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if (ret < 0)
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dev_warn(dev, "Populate child platform device fail\n");
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clk_disable_unprepare(mxc_isi->clk);
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mxc_isi_clk_disable(mxc_isi);
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platform_set_drvdata(pdev, mxc_isi);
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pm_runtime_enable(dev);
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dev_info(dev, "mxc_isi.%d registered successfully\n", mxc_isi->id);
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return 0;
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err:
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disp_mix_clks_enable(mxc_isi->clk_enable, false);
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disp_mix_sft_rstn(mxc_isi->soft_resetn, true);
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mxc_isi_clk_disable(mxc_isi);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
static int mxc_isi_remove(struct platform_device *pdev)
|
||||
|
|
@ -213,7 +461,9 @@ static int mxc_isi_runtime_suspend(struct device *dev)
|
|||
{
|
||||
struct mxc_isi_dev *mxc_isi = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(mxc_isi->clk);
|
||||
disp_mix_clks_enable(mxc_isi->clk_enable, false);
|
||||
mxc_isi_clk_disable(mxc_isi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -222,11 +472,15 @@ static int mxc_isi_runtime_resume(struct device *dev)
|
|||
struct mxc_isi_dev *mxc_isi = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(mxc_isi->clk);
|
||||
if (ret)
|
||||
ret = mxc_isi_clk_enable(mxc_isi);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s clk enable fail\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
disp_mix_sft_rstn(mxc_isi->soft_resetn, false);
|
||||
disp_mix_clks_enable(mxc_isi->clk_enable, true);
|
||||
|
||||
return (ret) ? ret : 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops mxc_isi_pm_ops = {
|
||||
|
|
@ -235,7 +489,8 @@ static const struct dev_pm_ops mxc_isi_pm_ops = {
|
|||
};
|
||||
|
||||
static const struct of_device_id mxc_isi_of_match[] = {
|
||||
{.compatible = "fsl,imx8-isi",},
|
||||
{.compatible = "fsl,imx8-isi", .data = &mxc_imx8_data },
|
||||
{.compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mxc_isi_of_match);
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@
|
|||
#include <media/v4l2-ctrls.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
#include <media/videobuf2-dma-contig.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
#include "imx8-common.h"
|
||||
|
||||
|
|
@ -41,6 +43,8 @@
|
|||
#define MXC_ISI_M2M "mxc-isi-m2m"
|
||||
#define MXC_MAX_PLANES 3
|
||||
|
||||
struct mxc_isi_dev;
|
||||
|
||||
enum mxc_isi_out_fmt {
|
||||
MXC_ISI_OUT_FMT_RGBA32 = 0x0,
|
||||
MXC_ISI_OUT_FMT_ABGR32,
|
||||
|
|
@ -188,6 +192,7 @@ struct mxc_isi_buffer {
|
|||
struct vb2_v4l2_buffer v4l2_buf;
|
||||
struct list_head list;
|
||||
struct frame_addr paddr;
|
||||
enum mxc_isi_buf_id id;
|
||||
bool discard;
|
||||
};
|
||||
|
||||
|
|
@ -223,6 +228,12 @@ struct mxc_isi_ctx {
|
|||
struct v4l2_fh fh;
|
||||
};
|
||||
|
||||
struct mxc_isi_dev_ops {
|
||||
int (*clk_get)(struct mxc_isi_dev *mxc_isi);
|
||||
int (*clk_enable)(struct mxc_isi_dev *mxc_isi);
|
||||
void (*clk_disable)(struct mxc_isi_dev *mxc_isi);
|
||||
};
|
||||
|
||||
struct mxc_isi_cap_dev {
|
||||
struct v4l2_subdev sd;
|
||||
struct video_device vdev;
|
||||
|
|
@ -265,8 +276,21 @@ struct mxc_isi_dev {
|
|||
struct mxc_isi_m2m_dev *isi_m2m;
|
||||
|
||||
struct platform_device *pdev;
|
||||
|
||||
/* clk for imx8qxp/qm platform */
|
||||
struct clk *clk;
|
||||
|
||||
/* clks for imx8mn platform */
|
||||
struct clk *clk_disp_axi;
|
||||
struct clk *clk_disp_apb;
|
||||
struct clk *clk_root_disp_axi;
|
||||
struct clk *clk_root_disp_apb;
|
||||
|
||||
const struct mxc_isi_dev_ops *ops;
|
||||
|
||||
struct reset_control *soft_resetn;
|
||||
struct reset_control *clk_enable;
|
||||
|
||||
struct mutex lock;
|
||||
spinlock_t slock;
|
||||
|
||||
|
|
@ -285,6 +309,8 @@ struct mxc_isi_dev {
|
|||
u32 pre_dec_x;
|
||||
u32 pre_dec_y;
|
||||
|
||||
u32 status;
|
||||
|
||||
u32 interface[MAX_PORTS];
|
||||
int id;
|
||||
|
||||
|
|
|
|||
|
|
@ -101,12 +101,13 @@ static void printk_pixelformat(char *prefix, int val)
|
|||
static bool is_rgb(u32 pix_fmt)
|
||||
{
|
||||
if ((pix_fmt == V4L2_PIX_FMT_RGB565) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_RGB24) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_RGB32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_BGR32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_RGB24) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_RGB32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_BGR32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_XRGB32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_XBGR32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_BGR24) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_BGR24) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_RGBA) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_ABGR32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_ARGB32))
|
||||
return true;
|
||||
|
|
@ -116,9 +117,10 @@ static bool is_rgb(u32 pix_fmt)
|
|||
|
||||
static bool is_yuv(u32 pix_fmt)
|
||||
{
|
||||
if ((pix_fmt == V4L2_PIX_FMT_YUYV) ||
|
||||
if ((pix_fmt == V4L2_PIX_FMT_YUYV) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_YUV32) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_YUV444M) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_YUV24) ||
|
||||
(pix_fmt == V4L2_PIX_FMT_NV12))
|
||||
return true;
|
||||
else
|
||||
|
|
@ -129,7 +131,7 @@ static void chain_buf(struct mxc_isi_dev *mxc_isi, struct mxc_isi_frame *frm)
|
|||
{
|
||||
u32 val;
|
||||
|
||||
if (frm->o_width > 2048) {
|
||||
if (frm->o_width > ISI_2K) {
|
||||
val = readl(mxc_isi->regs + CHNL_CTRL);
|
||||
val &= ~CHNL_CTRL_CHAIN_BUF_MASK;
|
||||
val |= (CHNL_CTRL_CHAIN_BUF_2_CHAIN << CHNL_CTRL_CHAIN_BUF_OFFSET);
|
||||
|
|
@ -174,16 +176,18 @@ void mxc_isi_channel_set_outbuf(struct mxc_isi_dev *mxc_isi,
|
|||
|
||||
val = readl(mxc_isi->regs + CHNL_OUT_BUF_CTRL);
|
||||
|
||||
if (framecount % 2 == 0) {
|
||||
if (framecount == 0 || ((mxc_isi->status & 0x100) && (framecount != 1))) {
|
||||
writel(paddr->y, mxc_isi->regs + CHNL_OUT_BUF1_ADDR_Y);
|
||||
writel(paddr->cb, mxc_isi->regs + CHNL_OUT_BUF1_ADDR_U);
|
||||
writel(paddr->cr, mxc_isi->regs + CHNL_OUT_BUF1_ADDR_V);
|
||||
val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK;
|
||||
} else if (framecount % 2 == 1) {
|
||||
buf->id = MXC_ISI_BUF1;
|
||||
} else if (framecount == 1 || mxc_isi->status & 0x200) {
|
||||
writel(paddr->y, mxc_isi->regs + CHNL_OUT_BUF2_ADDR_Y);
|
||||
writel(paddr->cb, mxc_isi->regs + CHNL_OUT_BUF2_ADDR_U);
|
||||
writel(paddr->cr, mxc_isi->regs + CHNL_OUT_BUF2_ADDR_V);
|
||||
val ^= CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK;
|
||||
buf->id = MXC_ISI_BUF2;
|
||||
}
|
||||
writel(val, mxc_isi->regs + CHNL_OUT_BUF_CTRL);
|
||||
}
|
||||
|
|
@ -701,7 +705,6 @@ void mxc_isi_m2m_config_src(struct mxc_isi_dev *mxc_isi,
|
|||
void mxc_isi_m2m_config_dst(struct mxc_isi_dev *mxc_isi,
|
||||
struct mxc_isi_frame *dst_f)
|
||||
{
|
||||
/*struct mxc_isi_frame *dst_f = &mxc_isi->isi_m2m->dst_f;*/
|
||||
u32 val;
|
||||
|
||||
/* out format */
|
||||
|
|
|
|||
|
|
@ -447,6 +447,13 @@
|
|||
#define CHNL_SCL_IMG_CFG_WIDTH_OFFSET 0
|
||||
#define CHNL_SCL_IMG_CFG_WIDTH_MASK 0x1FFF
|
||||
|
||||
/* Channel Flow Control Register */
|
||||
#define CHNL_FLOW_CTRL 0x9C
|
||||
#define CHNL_FLOW_CTRL_FC_DENOM_MASK 0xFF
|
||||
#define CHNL_FLOW_CTRL_FC_DENOM_OFFSET 0
|
||||
#define CHNL_FLOW_CTRL_FC_NUMER_MASK 0xFF0000
|
||||
#define CHNL_FLOW_CTRL_FC_NUMER_OFFSET 0
|
||||
|
||||
enum isi_csi_coeff {
|
||||
YUV2RGB = 0,
|
||||
RGB2YUV,
|
||||
|
|
|
|||
Loading…
Reference in New Issue