ARM: tegra: add LP1 support code for Tegra124
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just need to update the difference of the register address, then we can continue to share the code. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>hifive-unleashed-5.1
Joseph Lo
Stephen Warren
parent
92e94fe1cd
commit
f0c4ac1329
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@ -36,6 +36,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
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endif
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o
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endif
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@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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@ -105,6 +105,9 @@
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#define TEGRA_EMC1_BASE 0x7001A800
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#define TEGRA_EMC1_SIZE SZ_2K
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#define TEGRA124_EMC_BASE 0x7001B000
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#define TEGRA124_EMC_SIZE SZ_2K
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#define TEGRA_CSITE_BASE 0x70040000
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#define TEGRA_CSITE_SIZE SZ_256K
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@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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tegra_tear_down_cpu = tegra30_tear_down_cpu;
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break;
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}
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@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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tegra30_lp1_iram_hook();
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break;
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default:
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@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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tegra30_sleep_core_init();
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break;
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default:
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@ -408,8 +408,12 @@ _pll_m_c_x_done:
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cmp r10, #TEGRA30
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movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
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movteq r0, #:upper16:TEGRA_EMC_BASE
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movwne r0, #:lower16:TEGRA_EMC0_BASE
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movtne r0, #:upper16:TEGRA_EMC0_BASE
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cmp r10, #TEGRA114
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movweq r0, #:lower16:TEGRA_EMC0_BASE
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movteq r0, #:upper16:TEGRA_EMC0_BASE
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cmp r10, #TEGRA124
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movweq r0, #:lower16:TEGRA124_EMC_BASE
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movteq r0, #:upper16:TEGRA124_EMC_BASE
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exit_self_refresh:
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ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
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@ -556,6 +560,17 @@ tegra114_sdram_pad_address:
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.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
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tegra114_sdram_pad_adress_end:
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tegra124_sdram_pad_address:
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.word TEGRA124_EMC_BASE + EMC_CFG @0x0
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.word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
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.word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
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.word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
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.word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
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.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
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.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
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tegra124_sdram_pad_address_end:
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tegra30_sdram_pad_size:
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.word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
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@ -700,8 +715,13 @@ tegra30_sdram_self_refresh:
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cmp r10, #TEGRA30
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adreq r2, tegra30_sdram_pad_address
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ldreq r3, tegra30_sdram_pad_size
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adrne r2, tegra114_sdram_pad_address
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ldrne r3, tegra114_sdram_pad_size
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cmp r10, #TEGRA114
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adreq r2, tegra114_sdram_pad_address
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ldreq r3, tegra114_sdram_pad_size
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cmp r10, #TEGRA124
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adreq r2, tegra124_sdram_pad_address
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ldreq r3, tegra30_sdram_pad_size
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mov r9, #0
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padsave:
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@ -719,7 +739,10 @@ padsave_done:
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cmp r10, #TEGRA30
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ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
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ldrne r0, =TEGRA_EMC0_BASE
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cmp r10, #TEGRA114
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ldreq r0, =TEGRA_EMC0_BASE
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cmp r10, #TEGRA124
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ldreq r0, =TEGRA124_EMC_BASE
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enter_self_refresh:
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cmp r10, #TEGRA30
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