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MFD,mmc: tmio_mmc: make HCLK configurable

The Toshiba parts all have a 24 MHz HCLK, but HTC ASIC3 has a 24.576 MHz HCLK
and AMD Imageon w228x's HCLK is 80 MHz. With this patch, the MFD driver
provides the HCLK frequency to tmio_mmc via mfd_cell->driver_data.

Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Acked-by: Ian Molton <ian@mnementh.co.uk>
Acked-by: Samuel Ortiz <sameo@openedhand.com>
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
hifive-unleashed-5.1
Philipp Zabel 2009-06-04 20:12:31 +02:00 committed by Pierre Ossman
parent fdd858db71
commit f0e46cc497
5 changed files with 33 additions and 13 deletions

View File

@ -108,6 +108,10 @@ static int t7l66xb_mmc_disable(struct platform_device *mmc)
/*--------------------------------------------------------------------------*/
static const struct tmio_mmc_data t7166xb_mmc_data = {
.hclk = 24000000,
};
static const struct resource t7l66xb_mmc_resources[] = {
{
.start = 0x800,
@ -149,6 +153,7 @@ static struct mfd_cell t7l66xb_cells[] = {
.name = "tmio-mmc",
.enable = t7l66xb_mmc_enable,
.disable = t7l66xb_mmc_disable,
.driver_data = &t7166xb_mmc_data,
.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
.resources = t7l66xb_mmc_resources,
},

View File

@ -75,6 +75,10 @@ static int tc6387xb_mmc_disable(struct platform_device *mmc)
/*--------------------------------------------------------------------------*/
const static struct tmio_mmc_data tc6387xb_mmc_data = {
.hclk = 24000000,
};
static struct resource tc6387xb_mmc_resources[] = {
{
.start = 0x800,
@ -98,6 +102,7 @@ static struct mfd_cell tc6387xb_cells[] = {
.name = "tmio-mmc",
.enable = tc6387xb_mmc_enable,
.disable = tc6387xb_mmc_disable,
.driver_data = &tc6387xb_mmc_data,
.num_resources = ARRAY_SIZE(tc6387xb_mmc_resources),
.resources = tc6387xb_mmc_resources,
},

View File

@ -136,6 +136,10 @@ static int tc6393xb_nand_enable(struct platform_device *nand)
return 0;
}
const static struct tmio_mmc_data tc6393xb_mmc_data = {
.hclk = 24000000,
};
static struct resource __devinitdata tc6393xb_nand_resources[] = {
{
.start = 0x1000,
@ -351,6 +355,7 @@ static struct mfd_cell __devinitdata tc6393xb_cells[] = {
},
[TC6393XB_CELL_MMC] = {
.name = "tmio-mmc",
.driver_data = &tc6393xb_mmc_data,
.num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
.resources = tc6393xb_mmc_resources,
},

View File

@ -35,23 +35,14 @@
#include "tmio_mmc.h"
/*
* Fixme - documentation conflicts on what the clock values are for the
* various dividers.
* One document I have says that its a divisor of a 24MHz clock, another 33.
* This probably depends on HCLK for a given platform, so we may need to
* require HCLK be passed to us from the MFD core.
*
*/
static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
{
void __iomem *cnf = host->cnf;
void __iomem *ctl = host->ctl;
u32 clk = 0, clock;
u32 clk = 0, clock, f_min = host->mmc->f_min;
if (new_clock) {
for (clock = 46875, clk = 0x100; new_clock >= (clock<<1); ) {
for (clock = f_min, clk = 0x100; new_clock >= (clock<<1); ) {
clock <<= 1;
clk >>= 1;
}
@ -545,6 +536,7 @@ out:
static int __devinit tmio_mmc_probe(struct platform_device *dev)
{
struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
struct tmio_mmc_data *pdata;
struct resource *res_ctl, *res_cnf;
struct tmio_mmc_host *host;
struct mmc_host *mmc;
@ -560,6 +552,12 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
goto out;
}
pdata = cell->driver_data;
if (!pdata || !pdata->hclk) {
ret = -EINVAL;
goto out;
}
mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
if (!mmc)
goto out;
@ -578,8 +576,8 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
mmc->ops = &tmio_mmc_ops;
mmc->caps = MMC_CAP_4_BIT_DATA;
mmc->f_min = 46875; /* 24000000 / 512 */
mmc->f_max = 24000000;
mmc->f_max = pdata->hclk;
mmc->f_min = mmc->f_max / 512;
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
/* Enable the MMC/SD Control registers */

View File

@ -18,6 +18,13 @@
writew((val) >> 16, (addr) + 2); \
} while (0)
/*
* data for the MMC controller
*/
struct tmio_mmc_data {
unsigned int hclk;
};
/*
* data for the NAND controller
*/