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drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip

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There are some different bits between Rockchip and Exynos in register
"AUX_PD". This patch fixes the incorrect operations about it.

Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-12-enric.balletbo@collabora.com
This commit is contained in:
zain wang 2018-04-23 12:49:47 +02:00 committed by Andrzej Hajda
parent ccdc578b69
commit f12da6877e
2 changed files with 65 additions and 54 deletions
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117
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
View file

@ -248,76 +248,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
{
u32 reg;
u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
u32 mask;
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
phy_pd_addr = ANALOGIX_DP_PD;
switch (block) {
case AUX_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= AUX_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~AUX_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
mask = RK_AUX_PD;
else
mask = AUX_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH0_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH0_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH0_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH0_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH1_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH1_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH1_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH1_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH2_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH2_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH2_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH2_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH3_BLOCK:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH3_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH3_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
mask = CH3_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
break;
case ANALOG_TOTAL:
if (enable) {
reg = readl(dp->reg_base + phy_pd_addr);
reg |= DP_PHY_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~DP_PHY_PD;
writel(reg, dp->reg_base + phy_pd_addr);
}
/*
* There is no bit named DP_PHY_PD, so We used DP_INC_BG
* to power off everything instead of DP_PHY_PD in
* Rockchip
*/
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
mask = DP_INC_BG;
else
mask = DP_PHY_PD;
reg = readl(dp->reg_base + phy_pd_addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
writel(reg, dp->reg_base + phy_pd_addr);
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
usleep_range(10, 15);
break;
case POWER_ALL:
if (enable) {

2
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
View file

@ -345,7 +345,9 @@
#define DP_INC_BG (0x1 << 7)
#define DP_EXP_BG (0x1 << 6)
#define DP_PHY_PD (0x1 << 5)
#define RK_AUX_PD (0x1 << 5)
#define AUX_PD (0x1 << 4)
#define RK_PLL_PD (0x1 << 4)
#define CH3_PD (0x1 << 3)
#define CH2_PD (0x1 << 2)
#define CH1_PD (0x1 << 1)