PCI/ASPM: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify PCIe ASPM. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -125,21 +125,16 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
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static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
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{
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int pos;
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u16 reg16;
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struct pci_dev *child;
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struct pci_bus *linkbus = link->pdev->subordinate;
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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pos = pci_pcie_cap(child);
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if (!pos)
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return;
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pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
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if (enable)
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reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
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pcie_capability_set_word(child, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_CLKREQ_EN);
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else
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reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
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pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
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pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_CLKREQ_EN);
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}
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link->clkpm_enabled = !!enable;
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}
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@ -157,7 +152,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
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static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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int pos, capable = 1, enabled = 1;
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int capable = 1, enabled = 1;
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u32 reg32;
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u16 reg16;
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struct pci_dev *child;
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@ -165,16 +160,13 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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/* All functions should have the same cap and state, take the worst */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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pos = pci_pcie_cap(child);
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if (!pos)
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return;
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pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32);
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pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
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if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
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capable = 0;
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enabled = 0;
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break;
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}
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pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
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pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
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if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
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enabled = 0;
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}
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@ -190,7 +182,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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*/
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static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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{
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int ppos, cpos, same_clock = 1;
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int same_clock = 1;
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u16 reg16, parent_reg, child_reg[8];
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unsigned long start_jiffies;
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struct pci_dev *child, *parent = link->pdev;
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@ -203,46 +195,43 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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BUG_ON(!pci_is_pcie(child));
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/* Check downstream component if bit Slot Clock Configuration is 1 */
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cpos = pci_pcie_cap(child);
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pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16);
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pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_SLC))
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same_clock = 0;
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/* Check upstream component if bit Slot Clock Configuration is 1 */
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ppos = pci_pcie_cap(parent);
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pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_SLC))
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same_clock = 0;
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/* Configure downstream component, all functions */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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cpos = pci_pcie_cap(child);
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pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16);
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pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
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child_reg[PCI_FUNC(child->devfn)] = reg16;
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if (same_clock)
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reg16 |= PCI_EXP_LNKCTL_CCC;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
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pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
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}
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/* Configure upstream component */
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pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16);
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
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parent_reg = reg16;
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if (same_clock)
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reg16 |= PCI_EXP_LNKCTL_CCC;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Retrain link */
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reg16 |= PCI_EXP_LNKCTL_RL;
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pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Wait for link training end. Break out after waiting for timeout */
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start_jiffies = jiffies;
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for (;;) {
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pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
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@ -255,12 +244,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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/* Training failed. Restore common clock configurations */
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dev_printk(KERN_ERR, &parent->dev,
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"ASPM: Could not configure common clock\n");
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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cpos = pci_pcie_cap(child);
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pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
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child_reg[PCI_FUNC(child->devfn)]);
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}
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pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
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list_for_each_entry(child, &linkbus->devices, bus_list)
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pcie_capability_write_word(child, PCI_EXP_LNKCTL,
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child_reg[PCI_FUNC(child->devfn)]);
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
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}
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/* Convert L0s latency encoding to ns */
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@ -305,16 +292,14 @@ struct aspm_register_info {
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static void pcie_get_aspm_reg(struct pci_dev *pdev,
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struct aspm_register_info *info)
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{
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int pos;
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u16 reg16;
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u32 reg32;
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pos = pci_pcie_cap(pdev);
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pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
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pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
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info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
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info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
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info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
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pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
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info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
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}
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@ -420,7 +405,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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/* Get and check endpoint acceptable latencies */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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int pos;
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u32 reg32, encoding;
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struct aspm_latency *acceptable =
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&link->acceptable[PCI_FUNC(child->devfn)];
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@ -429,8 +413,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
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continue;
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pos = pci_pcie_cap(child);
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pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
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pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
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/* Calculate endpoint L0s acceptable latency */
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encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
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acceptable->l0s = calc_l0s_acceptable(encoding);
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@ -444,13 +427,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
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{
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u16 reg16;
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int pos = pci_pcie_cap(pdev);
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
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reg16 &= ~0x3;
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reg16 |= val;
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pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
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pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val);
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}
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static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
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@ -505,7 +482,6 @@ static void free_link_state(struct pcie_link_state *link)
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static int pcie_aspm_sanity_check(struct pci_dev *pdev)
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{
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struct pci_dev *child;
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int pos;
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u32 reg32;
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/*
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@ -513,8 +489,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
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* very strange. Disable ASPM for the whole slot
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*/
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list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
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pos = pci_pcie_cap(child);
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if (!pos)
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if (!pci_is_pcie(child))
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return -EINVAL;
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/*
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@ -530,7 +505,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
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* Disable ASPM for pre-1.1 PCIe device, we follow MS to use
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* RBER bit to determine if a function is 1.1 version device
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*/
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pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
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pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
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if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
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dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
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" on pre-1.1 PCIe device. You can enable it"
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