MIPS: pci-ar71xx: use dynamically allocated PCI controller structure
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4926/ Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Gabor Juhos
John Crispin
parent
12401fc28d
commit
f18118a868
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@ -48,8 +48,12 @@
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#define AR71XX_PCI_IRQ_COUNT 5
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static DEFINE_SPINLOCK(ar71xx_pci_lock);
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static void __iomem *ar71xx_pcicfg_base;
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struct ar71xx_pci_controller {
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void __iomem *cfg_base;
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spinlock_t lock;
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int irq;
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struct pci_controller pci_ctrl;
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};
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/* Byte lane enable bits */
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static const u8 ar71xx_pci_ble_table[4][4] = {
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@ -92,9 +96,18 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
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return ret;
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}
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static int ar71xx_pci_check_error(int quiet)
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static inline struct ar71xx_pci_controller *
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pci_bus_to_ar71xx_controller(struct pci_bus *bus)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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struct pci_controller *hose;
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hose = (struct pci_controller *) bus->sysdata;
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return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
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}
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static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
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{
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void __iomem *base = apc->cfg_base;
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u32 pci_err;
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u32 ahb_err;
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@ -129,9 +142,10 @@ static int ar71xx_pci_check_error(int quiet)
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return !!(ahb_err | pci_err);
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}
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static inline void ar71xx_pci_local_write(int where, int size, u32 value)
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static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
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int where, int size, u32 value)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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void __iomem *base = apc->cfg_base;
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u32 ad_cbe;
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value = value << (8 * (where & 3));
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@ -147,7 +161,8 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 cmd)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
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void __iomem *base = apc->cfg_base;
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u32 addr;
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addr = ar71xx_pci_bus_addr(bus, devfn, where);
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@ -156,13 +171,14 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
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__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
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base + AR71XX_PCI_REG_CFG_CBE);
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return ar71xx_pci_check_error(1);
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return ar71xx_pci_check_error(apc, 1);
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}
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static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
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void __iomem *base = apc->cfg_base;
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unsigned long flags;
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u32 data;
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int err;
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@ -171,7 +187,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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ret = PCIBIOS_SUCCESSFUL;
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data = ~0;
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spin_lock_irqsave(&ar71xx_pci_lock, flags);
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spin_lock_irqsave(&apc->lock, flags);
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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AR71XX_PCI_CFG_CMD_READ);
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@ -180,7 +196,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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else
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data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
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spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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spin_unlock_irqrestore(&apc->lock, flags);
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*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
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@ -190,7 +206,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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void __iomem *base = ar71xx_pcicfg_base;
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struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
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void __iomem *base = apc->cfg_base;
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unsigned long flags;
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int err;
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int ret;
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@ -198,7 +215,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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value = value << (8 * (where & 3));
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ret = PCIBIOS_SUCCESSFUL;
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spin_lock_irqsave(&ar71xx_pci_lock, flags);
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spin_lock_irqsave(&apc->lock, flags);
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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AR71XX_PCI_CFG_CMD_WRITE);
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@ -207,7 +224,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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else
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__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
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spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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spin_unlock_irqrestore(&apc->lock, flags);
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return ret;
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}
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@ -231,12 +248,6 @@ static struct resource ar71xx_pci_mem_resource = {
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ar71xx_pci_controller = {
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.pci_ops = &ar71xx_pci_ops,
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.mem_resource = &ar71xx_pci_mem_resource,
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.io_resource = &ar71xx_pci_io_resource,
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};
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static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ath79_reset_base;
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@ -294,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_chip = {
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.irq_mask_ack = ar71xx_pci_irq_mask,
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};
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static void ar71xx_pci_irq_init(int irq)
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static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
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{
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void __iomem *base = ath79_reset_base;
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int i;
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@ -309,7 +320,7 @@ static void ar71xx_pci_irq_init(int irq)
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irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
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irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
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}
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static void ar71xx_pci_reset(void)
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@ -336,20 +347,27 @@ static void ar71xx_pci_reset(void)
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static int ar71xx_pci_probe(struct platform_device *pdev)
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{
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struct ar71xx_pci_controller *apc;
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struct resource *res;
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int irq;
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u32 t;
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apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
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GFP_KERNEL);
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if (!apc)
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return -ENOMEM;
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spin_lock_init(&apc->lock);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
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if (!res)
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return -EINVAL;
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ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!ar71xx_pcicfg_base)
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apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
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if (!apc->cfg_base)
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return -ENOMEM;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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apc->irq = platform_get_irq(pdev, 0);
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if (apc->irq < 0)
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return -EINVAL;
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ar71xx_pci_reset();
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@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platform_device *pdev)
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/* setup COMMAND register */
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t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
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| PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
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ar71xx_pci_local_write(PCI_COMMAND, 4, t);
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ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
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/* clear bus errors */
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ar71xx_pci_check_error(1);
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ar71xx_pci_check_error(apc, 1);
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ar71xx_pci_irq_init(irq);
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ar71xx_pci_irq_init(apc);
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register_pci_controller(&ar71xx_pci_controller);
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apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
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apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
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apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
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register_pci_controller(&apc->pci_ctrl);
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return 0;
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}
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