iommu/vt-d: Add a check for 5-level paging support
Add a check to verify IOMMU 5-level paging support. If the CPU supports supports 5-level paging but the IOMMU does not support it then disable SVM by not allocating PASID tables. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>hifive-unleashed-5.1
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59103caa68
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f1ac10c24e
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@ -45,6 +45,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
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!cap_fl1gp_support(iommu->cap))
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!cap_fl1gp_support(iommu->cap))
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return -EINVAL;
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return -EINVAL;
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if (cpu_feature_enabled(X86_FEATURE_LA57) &&
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!cap_5lp_support(iommu->cap))
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return -EINVAL;
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/* Start at 2 because it's defined as 2^(1+PSS) */
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/* Start at 2 because it's defined as 2^(1+PSS) */
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iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
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iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
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@ -83,6 +83,7 @@
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/*
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/*
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* Decoding Capability Register
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* Decoding Capability Register
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*/
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*/
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#define cap_5lp_support(c) (((c) >> 60) & 1)
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#define cap_pi_support(c) (((c) >> 59) & 1)
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#define cap_pi_support(c) (((c) >> 59) & 1)
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#define cap_fl1gp_support(c) (((c) >> 56) & 1)
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#define cap_fl1gp_support(c) (((c) >> 56) & 1)
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#define cap_read_drain(c) (((c) >> 55) & 1)
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#define cap_read_drain(c) (((c) >> 55) & 1)
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