Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar:
"The main changes in this tree are:
- fix and update Intel Quark [Galileo] SoC platform support
- update IOSF chipset side band interface and make it available via
debugfs
- enable HPETs on Soekris net6501 and other e6xx based systems"
* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86: Add cpu_detect_cache_sizes to init_intel() add Quark legacy_cache()
x86: Quark: Comment setup_arch() to document TLB/PGE bug
x86/intel/quark: Switch off CR4.PGE so TLB flush uses CR3 instead
x86/platform/intel/iosf: Add debugfs config option for IOSF
x86/platform/intel/iosf: Add better description of IOSF driver in config
x86/platform/intel/iosf: Add Braswell PCI ID
x86/platform/pmc_atom: Fix warning when CONFIG_DEBUG_FS=n
x86: HPET force enable for e6xx based systems
x86/iosf: Add debugfs support
x86/iosf: Add Kconfig prompt for IOSF_MBI selection
hifive-unleashed-5.1
Linus Torvalds
commit
f1bfbd984b
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@ -491,6 +491,36 @@ config X86_INTEL_LPSS
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things like clock tree (common clock framework) and pincontrol
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which are needed by the LPSS peripheral drivers.
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config IOSF_MBI
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tristate "Intel SoC IOSF Sideband support for SoC platforms"
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depends on PCI
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---help---
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This option enables sideband register access support for Intel SoC
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platforms. On these platforms the IOSF sideband is used in lieu of
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MSR's for some register accesses, mostly but not limited to thermal
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and power. Drivers may query the availability of this device to
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determine if they need the sideband in order to work on these
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platforms. The sideband is available on the following SoC products.
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This list is not meant to be exclusive.
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- BayTrail
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- Braswell
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- Quark
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You should say Y if you are running a kernel on one of these SoC's.
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config IOSF_MBI_DEBUG
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bool "Enable IOSF sideband access through debugfs"
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depends on IOSF_MBI && DEBUG_FS
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---help---
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Select this option to expose the IOSF sideband access registers (MCR,
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MDR, MCRX) through debugfs to write and read register information from
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different units on the SoC. This is most useful for obtaining device
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state information for debug and analysis. As this is a general access
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mechanism, users of this option would have specific knowledge of the
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device they want to access.
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If you don't require the option or are in doubt, say N.
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config X86_RDC321X
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bool "RDC R-321x SoC"
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depends on X86_32
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@ -2454,11 +2484,6 @@ config X86_DMA_REMAP
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bool
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depends on STA2X11
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config IOSF_MBI
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tristate
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default m
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depends on PCI
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config PMC_ATOM
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def_bool y
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depends on PCI
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@ -144,6 +144,21 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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setup_clear_cpu_cap(X86_FEATURE_ERMS);
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}
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}
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/*
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* Intel Quark Core DevMan_001.pdf section 6.4.11
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* "The operating system also is required to invalidate (i.e., flush)
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* the TLB when any changes are made to any of the page table entries.
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* The operating system must reload CR3 to cause the TLB to be flushed"
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*
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* As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
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* be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
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* to be modified
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*/
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if (c->x86 == 5 && c->x86_model == 9) {
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pr_info("Disabling PGE capability bit\n");
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setup_clear_cpu_cap(X86_FEATURE_PGE);
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}
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}
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#ifdef CONFIG_X86_32
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@ -382,6 +397,13 @@ static void init_intel(struct cpuinfo_x86 *c)
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}
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l2 = init_intel_cacheinfo(c);
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/* Detect legacy cache sizes if init_intel_cacheinfo did not */
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if (l2 == 0) {
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cpu_detect_cache_sizes(c);
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l2 = c->x86_cache_size;
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}
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if (c->cpuid_level > 9) {
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unsigned eax = cpuid_eax(10);
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/* Check for version and the number of counters */
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@ -485,6 +507,13 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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*/
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if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
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size = 256;
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/*
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* Intel Quark SoC X1000 contains a 4-way set associative
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* 16K cache with a 16 byte cache line and 256 lines per tag
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*/
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if ((c->x86 == 5) && (c->x86_model == 9))
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size = 16;
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return size;
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}
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#endif
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@ -686,7 +715,8 @@ static const struct cpu_dev intel_cpu_dev = {
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[3] = "OverDrive PODP5V83",
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[4] = "Pentium MMX",
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[7] = "Mobile Pentium 75 - 200",
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[8] = "Mobile Pentium MMX"
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[8] = "Mobile Pentium MMX",
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[9] = "Quark SoC X1000",
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}
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},
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{ .family = 6, .model_names =
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@ -22,10 +22,13 @@
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/debugfs.h>
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#include <linux/capability.h>
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#include <asm/iosf_mbi.h>
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#define PCI_DEVICE_ID_BAYTRAIL 0x0F00
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#define PCI_DEVICE_ID_BRASWELL 0x2280
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#define PCI_DEVICE_ID_QUARK_X1000 0x0958
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static DEFINE_SPINLOCK(iosf_mbi_lock);
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@ -187,6 +190,89 @@ bool iosf_mbi_available(void)
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}
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EXPORT_SYMBOL(iosf_mbi_available);
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#ifdef CONFIG_IOSF_MBI_DEBUG
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static u32 dbg_mdr;
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static u32 dbg_mcr;
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static u32 dbg_mcrx;
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static int mcr_get(void *data, u64 *val)
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{
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*val = *(u32 *)data;
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return 0;
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}
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static int mcr_set(void *data, u64 val)
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{
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u8 command = ((u32)val & 0xFF000000) >> 24,
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port = ((u32)val & 0x00FF0000) >> 16,
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offset = ((u32)val & 0x0000FF00) >> 8;
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int err;
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*(u32 *)data = val;
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if (!capable(CAP_SYS_RAWIO))
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return -EACCES;
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if (command & 1u)
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err = iosf_mbi_write(port,
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command,
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dbg_mcrx | offset,
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dbg_mdr);
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else
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err = iosf_mbi_read(port,
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command,
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dbg_mcrx | offset,
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&dbg_mdr);
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return err;
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}
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DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");
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static struct dentry *iosf_dbg;
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static void iosf_sideband_debug_init(void)
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{
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struct dentry *d;
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iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
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if (IS_ERR_OR_NULL(iosf_dbg))
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return;
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/* mdr */
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d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
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if (IS_ERR_OR_NULL(d))
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goto cleanup;
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/* mcrx */
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debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
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if (IS_ERR_OR_NULL(d))
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goto cleanup;
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/* mcr - initiates mailbox tranaction */
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debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
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if (IS_ERR_OR_NULL(d))
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goto cleanup;
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return;
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cleanup:
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debugfs_remove_recursive(d);
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}
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static void iosf_debugfs_init(void)
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{
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iosf_sideband_debug_init();
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}
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static void iosf_debugfs_remove(void)
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{
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debugfs_remove_recursive(iosf_dbg);
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}
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#else
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static inline void iosf_debugfs_init(void) { }
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static inline void iosf_debugfs_remove(void) { }
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#endif /* CONFIG_IOSF_MBI_DEBUG */
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static int iosf_mbi_probe(struct pci_dev *pdev,
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const struct pci_device_id *unused)
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{
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@ -204,6 +290,7 @@ static int iosf_mbi_probe(struct pci_dev *pdev,
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static const struct pci_device_id iosf_mbi_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
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{ 0, },
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};
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@ -217,11 +304,15 @@ static struct pci_driver iosf_mbi_pci_driver = {
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static int __init iosf_mbi_init(void)
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{
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iosf_debugfs_init();
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return pci_register_driver(&iosf_mbi_pci_driver);
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}
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static void __exit iosf_mbi_exit(void)
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{
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iosf_debugfs_remove();
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pci_unregister_driver(&iosf_mbi_pci_driver);
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if (mbi_pdev) {
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pci_dev_put(mbi_pdev);
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|
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@ -235,6 +235,11 @@ err:
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pmc_dbgfs_unregister(pmc);
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return -ENODEV;
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}
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#else
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static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
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{
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return 0;
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}
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#endif /* CONFIG_DEBUG_FS */
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static int pmc_setup_dev(struct pci_dev *pdev)
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@ -262,14 +267,12 @@ static int pmc_setup_dev(struct pci_dev *pdev)
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/* PMC hardware registers setup */
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pmc_hw_reg_setup(pmc);
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#ifdef CONFIG_DEBUG_FS
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ret = pmc_dbgfs_register(pmc, pdev);
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if (ret) {
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iounmap(pmc->regmap);
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return ret;
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}
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#endif /* CONFIG_DEBUG_FS */
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return 0;
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return ret;
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}
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/*
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|
|
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@ -497,6 +497,24 @@ void force_hpet_resume(void)
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}
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}
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/*
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||||
* According to the datasheet e6xx systems have the HPET hardwired to
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* 0xfed00000
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||||
*/
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||||
static void e6xx_force_enable_hpet(struct pci_dev *dev)
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{
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if (hpet_address || force_hpet_address)
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||||
return;
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||||
force_hpet_address = 0xFED00000;
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force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
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dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
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||||
"0x%lx\n", force_hpet_address);
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||||
return;
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
|
||||
e6xx_force_enable_hpet);
|
||||
|
||||
/*
|
||||
* HPET MSI on some boards (ATI SB700/SB800) has side effect on
|
||||
* floppy DMA. Disable HPET MSI on such platforms.
|
||||
|
|
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|||
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|
@ -879,6 +879,15 @@ void __init setup_arch(char **cmdline_p)
|
|||
KERNEL_PGD_PTRS);
|
||||
|
||||
load_cr3(swapper_pg_dir);
|
||||
/*
|
||||
* Note: Quark X1000 CPUs advertise PGE incorrectly and require
|
||||
* a cr3 based tlb flush, so the following __flush_tlb_all()
|
||||
* will not flush anything because the cpu quirk which clears
|
||||
* X86_FEATURE_PGE has not been invoked yet. Though due to the
|
||||
* load_cr3() above the TLB has been flushed already. The
|
||||
* quirk is invoked before subsequent calls to __flush_tlb_all()
|
||||
* so proper operation is guaranteed.
|
||||
*/
|
||||
__flush_tlb_all();
|
||||
#else
|
||||
printk(KERN_INFO "Command line: %s\n", boot_command_line);
|
||||
|
|
|
|||
|
|
@ -2878,6 +2878,7 @@
|
|||
#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
|
||||
#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119
|
||||
#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a
|
||||
#define PCI_DEVICE_ID_INTEL_E6XX_CU 0x8183
|
||||
#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186
|
||||
#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
|
||||
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
|
||||
|
|
|
|||
Loading…
Reference in New Issue