Samsung S2R PM updates for v3.15
From Tomasz Figa: This series reworks suspend/resume handling of Samsung clock drivers to cover more SoC specific aspects that are beyond simple register save and restore. The goal is to have all the suspend/resume code that touches the clock controller in single place, which is the clock driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTE9NAAAoJEA0Cl+kVi2xqLHEQAKtWQKYXNIkGtTpjs5Nf+3Jv 9CZpvAHAQ7Lto1Euewo3KSF0JBo9o3TnOUbu6AUuo9UQV9G0TrRTpme4nlWpf0IF UdCSb7px3tsd1pcOS2FyI9I+DBZ9qbk/ytJV6K/KWjvkp+sFfKtDO3ockVQLy/oF zR7vB4kF9SSICPk7I4lHvs1JV8z/do8V7PTMOywDPUAYpw5pwSLovFXLOjKDvOCC w/Q1X0fqrVCPBbKpnAfez2dJHfL/iQXCa5vD5T0HeVgMOUgKA7MgLeAbZa+vsFVd NKOya+eAn8vGZxxC9eX2F5XcT+fvs+7aLaHmW5Rw8mg4Dh8F0+8OyFYOpZxFr58P N+jQPlGnOhgPw/pGmtzgktyvNlB/7iRMXHnUksQbmtz47nxQAZTe/USTSWj0nUUy X21+8qI+RJI5UURvB4AH7pY7tmNdY4LjJsB1MgwlY3EIf9AN9Str1IkFxV3kylGK V67uQv7VKRBz2IKMsgTjNhriSGIoIV+0pnOj1l/zz+Rs1S0sVQwuDqPTSzPezBOS vWqTQOa6uGQvMzW8lAAyhdpxt+nWxUXsB9ZilqfDLSrmQHngaF5dnUJp98zwt2yX xRE/R329i76uls3W+HBHZU4TfAi724NJbct0/Ieoa4oz6ZFcweL8oObm8s264mId 3EpHFU0ju7owDiP+FBXV =82IK -----END PGP SIGNATURE----- Merge tag 'samsung-pm-1' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Merge "Samsung S2R PM updates for v3.15" from Kukjin Kim: From Tomasz Figa: This series reworks suspend/resume handling of Samsung clock drivers to cover more SoC specific aspects that are beyond simple register save and restore. The goal is to have all the suspend/resume code that touches the clock controller in single place, which is the clock driver. * tag 'samsung-pm-1' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Drop legacy Exynos4 clock suspend/resume code clk: samsung: exynos4: Add remaining suspend/resume handling clk: samsung: Drop old suspend/resume code clk: samsung: s3c64xx: Move suspend/resume handling to SoC driver clk: samsung: exynos5420: Move suspend/resume handling to SoC driver clk: samsung: exynos5250: Move suspend/resume handling to SoC driver clk: samsung: exynos4: Move suspend/resume handling to SoC driver clk: samsung: Provide common helpers for register save/restore clk: exynos4: Remove remnants of non-DT support Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
f1d7d8c86b
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@ -35,56 +35,6 @@
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#include "common.h"
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#include "regs-pmu.h"
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#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010)
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#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020)
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#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110)
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#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114)
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#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120)
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#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124)
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#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310)
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#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320)
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#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324)
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#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334)
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#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C)
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#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340)
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#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350)
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#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354)
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#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300)
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#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338)
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static const struct sleep_save exynos4_set_clksrc[] = {
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{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
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{ .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
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{ .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
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{ .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
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};
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static const struct sleep_save exynos4210_set_clksrc[] = {
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{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
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};
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static struct sleep_save exynos4_epll_save[] = {
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SAVE_ITEM(EXYNOS4_EPLL_CON0),
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SAVE_ITEM(EXYNOS4_EPLL_CON1),
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};
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static struct sleep_save exynos4_vpll_save[] = {
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SAVE_ITEM(EXYNOS4_VPLL_CON0),
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SAVE_ITEM(EXYNOS4_VPLL_CON1),
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};
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static struct sleep_save exynos5_sys_save[] = {
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SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
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};
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@ -124,10 +74,7 @@ static void exynos_pm_prepare(void)
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (!soc_is_exynos5250()) {
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s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
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s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
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} else {
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if (soc_is_exynos5250()) {
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s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
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/* Disable USE_RETENTION of JPEG_MEM_OPTION */
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tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
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@ -143,15 +90,6 @@ static void exynos_pm_prepare(void)
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/* ensure at least INFORM0 has the resume address */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
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/* Before enter central sequence mode, clock src register have to set */
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if (!soc_is_exynos5250())
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s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
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if (soc_is_exynos4210())
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s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
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}
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static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
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@ -162,73 +100,6 @@ static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
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return 0;
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}
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static unsigned long pll_base_rate;
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static void exynos4_restore_pll(void)
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{
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unsigned long pll_con, locktime, lockcnt;
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unsigned long pll_in_rate;
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unsigned int p_div, epll_wait = 0, vpll_wait = 0;
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if (pll_base_rate == 0)
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return;
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pll_in_rate = pll_base_rate;
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/* EPLL */
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pll_con = exynos4_epll_save[0].val;
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if (pll_con & (1 << 31)) {
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pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
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p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
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pll_in_rate /= 1000000;
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locktime = (3000 / pll_in_rate) * p_div;
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lockcnt = locktime * 10000 / (10000 / pll_in_rate);
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__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
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s3c_pm_do_restore_core(exynos4_epll_save,
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ARRAY_SIZE(exynos4_epll_save));
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epll_wait = 1;
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}
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pll_in_rate = pll_base_rate;
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/* VPLL */
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pll_con = exynos4_vpll_save[0].val;
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if (pll_con & (1 << 31)) {
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pll_in_rate /= 1000000;
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/* 750us */
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locktime = 750;
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lockcnt = locktime * 10000 / (10000 / pll_in_rate);
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__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
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s3c_pm_do_restore_core(exynos4_vpll_save,
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ARRAY_SIZE(exynos4_vpll_save));
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vpll_wait = 1;
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}
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/* Wait PLL locking */
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do {
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if (epll_wait) {
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pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
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if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
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epll_wait = 0;
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}
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if (vpll_wait) {
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pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
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if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
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vpll_wait = 0;
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}
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} while (epll_wait || vpll_wait);
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}
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static struct subsys_interface exynos_pm_interface = {
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.name = "exynos_pm",
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.subsys = &exynos_subsys,
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@ -237,7 +108,6 @@ static struct subsys_interface exynos_pm_interface = {
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static __init int exynos_pm_drvinit(void)
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{
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struct clk *pll_base;
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unsigned int tmp;
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if (soc_is_exynos5440())
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@ -251,15 +121,6 @@ static __init int exynos_pm_drvinit(void)
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tmp |= ((0xFF << 8) | (0x1F << 1));
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__raw_writel(tmp, S5P_WAKEUP_MASK);
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if (!soc_is_exynos5250()) {
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pll_base = clk_get(NULL, "xtal");
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if (!IS_ERR(pll_base)) {
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pll_base_rate = clk_get_rate(pll_base);
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clk_put(pll_base);
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}
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}
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return subsys_interface_register(&exynos_pm_interface);
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}
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arch_initcall(exynos_pm_drvinit);
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@ -343,13 +204,8 @@ static void exynos_pm_resume(void)
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (!soc_is_exynos5250()) {
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exynos4_restore_pll();
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#ifdef CONFIG_SMP
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if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
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scu_enable(S5P_VA_SCU);
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#endif
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}
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early_wakeup:
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@ -16,6 +16,7 @@
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include "clk.h"
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@ -130,6 +131,17 @@ enum exynos4_plls {
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nr_plls /* number of PLLs */
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};
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static void __iomem *reg_base;
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static enum exynos4_soc exynos4_soc;
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/*
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* Support for CMU save/restore across system suspends
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*/
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *exynos4_save_common;
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static struct samsung_clk_reg_dump *exynos4_save_soc;
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static struct samsung_clk_reg_dump *exynos4_save_pll;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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@ -154,6 +166,17 @@ static unsigned long exynos4x12_clk_save[] __initdata = {
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E4X12_MPLL_CON0,
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};
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static unsigned long exynos4_clk_pll_regs[] __initdata = {
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EPLL_LOCK,
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VPLL_LOCK,
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EPLL_CON0,
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EPLL_CON1,
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EPLL_CON2,
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VPLL_CON0,
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VPLL_CON1,
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VPLL_CON2,
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};
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static unsigned long exynos4_clk_regs[] __initdata = {
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SRC_LEFTBUS,
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DIV_LEFTBUS,
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@ -161,12 +184,6 @@ static unsigned long exynos4_clk_regs[] __initdata = {
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SRC_RIGHTBUS,
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DIV_RIGHTBUS,
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GATE_IP_RIGHTBUS,
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EPLL_CON0,
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EPLL_CON1,
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EPLL_CON2,
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VPLL_CON0,
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VPLL_CON1,
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VPLL_CON2,
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SRC_TOP0,
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SRC_TOP1,
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SRC_CAM,
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@ -227,6 +244,124 @@ static unsigned long exynos4_clk_regs[] __initdata = {
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GATE_IP_CPU,
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};
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static const struct samsung_clk_reg_dump src_mask_suspend[] = {
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{ .offset = SRC_MASK_TOP, .value = 0x00000001, },
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{ .offset = SRC_MASK_CAM, .value = 0x11111111, },
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{ .offset = SRC_MASK_TV, .value = 0x00000111, },
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{ .offset = SRC_MASK_LCD0, .value = 0x00001111, },
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{ .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
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{ .offset = SRC_MASK_FSYS, .value = 0x01011111, },
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{ .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
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{ .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
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{ .offset = SRC_MASK_DMC, .value = 0x00010000, },
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};
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static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
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{ .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
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};
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#define PLL_ENABLED (1 << 31)
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#define PLL_LOCKED (1 << 29)
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static void exynos4_clk_wait_for_pll(u32 reg)
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{
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u32 pll_con;
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pll_con = readl(reg_base + reg);
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if (!(pll_con & PLL_ENABLED))
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return;
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while (!(pll_con & PLL_LOCKED)) {
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cpu_relax();
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pll_con = readl(reg_base + reg);
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}
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}
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static int exynos4_clk_suspend(void)
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{
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samsung_clk_save(reg_base, exynos4_save_common,
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ARRAY_SIZE(exynos4_clk_regs));
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samsung_clk_save(reg_base, exynos4_save_pll,
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ARRAY_SIZE(exynos4_clk_pll_regs));
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if (exynos4_soc == EXYNOS4210) {
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samsung_clk_save(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4210_clk_save));
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samsung_clk_restore(reg_base, src_mask_suspend_e4210,
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ARRAY_SIZE(src_mask_suspend_e4210));
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} else {
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samsung_clk_save(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4x12_clk_save));
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}
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samsung_clk_restore(reg_base, src_mask_suspend,
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ARRAY_SIZE(src_mask_suspend));
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return 0;
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}
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static void exynos4_clk_resume(void)
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{
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samsung_clk_restore(reg_base, exynos4_save_pll,
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ARRAY_SIZE(exynos4_clk_pll_regs));
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exynos4_clk_wait_for_pll(EPLL_CON0);
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exynos4_clk_wait_for_pll(VPLL_CON0);
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samsung_clk_restore(reg_base, exynos4_save_common,
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ARRAY_SIZE(exynos4_clk_regs));
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if (exynos4_soc == EXYNOS4210)
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samsung_clk_restore(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4210_clk_save));
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else
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samsung_clk_restore(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4x12_clk_save));
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}
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static struct syscore_ops exynos4_clk_syscore_ops = {
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.suspend = exynos4_clk_suspend,
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.resume = exynos4_clk_resume,
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};
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static void exynos4_clk_sleep_init(void)
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{
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exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs,
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ARRAY_SIZE(exynos4_clk_regs));
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if (!exynos4_save_common)
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goto err_warn;
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if (exynos4_soc == EXYNOS4210)
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exynos4_save_soc = samsung_clk_alloc_reg_dump(
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exynos4210_clk_save,
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ARRAY_SIZE(exynos4210_clk_save));
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else
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exynos4_save_soc = samsung_clk_alloc_reg_dump(
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exynos4x12_clk_save,
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ARRAY_SIZE(exynos4x12_clk_save));
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if (!exynos4_save_soc)
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goto err_common;
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|
||||
exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs,
|
||||
ARRAY_SIZE(exynos4_clk_pll_regs));
|
||||
if (!exynos4_save_pll)
|
||||
goto err_soc;
|
||||
|
||||
register_syscore_ops(&exynos4_clk_syscore_ops);
|
||||
return;
|
||||
|
||||
err_soc:
|
||||
kfree(exynos4_save_soc);
|
||||
err_common:
|
||||
kfree(exynos4_save_common);
|
||||
err_warn:
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
}
|
||||
#else
|
||||
static void exynos4_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
|
||||
PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
|
||||
|
|
@ -908,12 +1043,13 @@ static unsigned long exynos4_get_xom(void)
|
|||
return xom;
|
||||
}
|
||||
|
||||
static void __init exynos4_clk_register_finpll(unsigned long xom)
|
||||
static void __init exynos4_clk_register_finpll(void)
|
||||
{
|
||||
struct samsung_fixed_rate_clock fclk;
|
||||
struct clk *clk;
|
||||
unsigned long finpll_f = 24000000;
|
||||
char *parent_name;
|
||||
unsigned int xom = exynos4_get_xom();
|
||||
|
||||
parent_name = xom & 1 ? "xusbxti" : "xxti";
|
||||
clk = clk_get(NULL, parent_name);
|
||||
|
|
@ -1038,27 +1174,21 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
|
|||
|
||||
/* register exynos4 clocks */
|
||||
static void __init exynos4_clk_init(struct device_node *np,
|
||||
enum exynos4_soc exynos4_soc,
|
||||
void __iomem *reg_base, unsigned long xom)
|
||||
enum exynos4_soc soc)
|
||||
{
|
||||
exynos4_soc = soc;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
if (exynos4_soc == EXYNOS4210)
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS,
|
||||
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
|
||||
exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
|
||||
else
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS,
|
||||
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
|
||||
exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
|
||||
samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
|
||||
ext_clk_match);
|
||||
|
||||
exynos4_clk_register_finpll(xom);
|
||||
exynos4_clk_register_finpll();
|
||||
|
||||
if (exynos4_soc == EXYNOS4210) {
|
||||
samsung_clk_register_mux(exynos4210_mux_early,
|
||||
|
|
@ -1125,6 +1255,8 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
samsung_clk_register_alias(exynos4_aliases,
|
||||
ARRAY_SIZE(exynos4_aliases));
|
||||
|
||||
exynos4_clk_sleep_init();
|
||||
|
||||
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
|
||||
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
|
||||
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
|
||||
|
|
@ -1136,12 +1268,12 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
|
||||
static void __init exynos4210_clk_init(struct device_node *np)
|
||||
{
|
||||
exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom());
|
||||
exynos4_clk_init(np, EXYNOS4210);
|
||||
}
|
||||
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
|
||||
|
||||
static void __init exynos4412_clk_init(struct device_node *np)
|
||||
{
|
||||
exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom());
|
||||
exynos4_clk_init(np, EXYNOS4X12);
|
||||
}
|
||||
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
|
|
@ -85,6 +86,11 @@ enum exynos5250_plls {
|
|||
nr_plls /* number of PLLs */
|
||||
};
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *exynos5250_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -137,6 +143,41 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
|
|||
GATE_IP_ACP,
|
||||
};
|
||||
|
||||
static int exynos5250_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, exynos5250_save,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos5250_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, exynos5250_save,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos5250_clk_syscore_ops = {
|
||||
.suspend = exynos5250_clk_suspend,
|
||||
.resume = exynos5250_clk_resume,
|
||||
};
|
||||
|
||||
static void exynos5250_clk_sleep_init(void)
|
||||
{
|
||||
exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
if (!exynos5250_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&exynos5250_clk_syscore_ops);
|
||||
}
|
||||
#else
|
||||
static void exynos5250_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
|
||||
PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
|
||||
|
|
@ -645,8 +686,6 @@ static struct of_device_id ext_clk_match[] __initdata = {
|
|||
/* register exynox5250 clocks */
|
||||
static void __init exynos5250_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
|
|
@ -655,9 +694,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
panic("%s: unable to determine soc\n", __func__);
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS,
|
||||
exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
|
||||
NULL, 0);
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
|
||||
ext_clk_match);
|
||||
|
|
@ -685,6 +722,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
samsung_clk_register_gate(exynos5250_gate_clks,
|
||||
ARRAY_SIZE(exynos5250_gate_clks));
|
||||
|
||||
exynos5250_clk_sleep_init();
|
||||
|
||||
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
|
||||
_get_rate("div_arm2"));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
|
|
@ -108,6 +109,11 @@ enum exynos5420_plls {
|
|||
nr_plls /* number of PLLs */
|
||||
};
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *exynos5420_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -174,6 +180,41 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
|
|||
DIV_KFC0,
|
||||
};
|
||||
|
||||
static int exynos5420_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, exynos5420_save,
|
||||
ARRAY_SIZE(exynos5420_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos5420_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, exynos5420_save,
|
||||
ARRAY_SIZE(exynos5420_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos5420_clk_syscore_ops = {
|
||||
.suspend = exynos5420_clk_suspend,
|
||||
.resume = exynos5420_clk_resume,
|
||||
};
|
||||
|
||||
static void exynos5420_clk_sleep_init(void)
|
||||
{
|
||||
exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs,
|
||||
ARRAY_SIZE(exynos5420_clk_regs));
|
||||
if (!exynos5420_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&exynos5420_clk_syscore_ops);
|
||||
}
|
||||
#else
|
||||
static void exynos5420_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* list of all parent clocks */
|
||||
PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll",
|
||||
"sclk_mpll", "sclk_spll" };
|
||||
|
|
@ -737,8 +778,6 @@ static struct of_device_id ext_clk_match[] __initdata = {
|
|||
/* register exynos5420 clocks */
|
||||
static void __init exynos5420_clk_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
|
|
@ -747,9 +786,7 @@ static void __init exynos5420_clk_init(struct device_node *np)
|
|||
panic("%s: unable to determine soc\n", __func__);
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS,
|
||||
exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
|
||||
NULL, 0);
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
|
||||
ext_clk_match);
|
||||
|
|
@ -765,5 +802,7 @@ static void __init exynos5420_clk_init(struct device_node *np)
|
|||
ARRAY_SIZE(exynos5420_div_clks));
|
||||
samsung_clk_register_gate(exynos5420_gate_clks,
|
||||
ARRAY_SIZE(exynos5420_gate_clks));
|
||||
|
||||
exynos5420_clk_sleep_init();
|
||||
}
|
||||
CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ static void __init exynos5440_clk_init(struct device_node *np)
|
|||
return;
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0);
|
||||
samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
||||
samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
|
||||
ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
|
||||
|
||||
|
|
@ -61,6 +62,13 @@ enum s3c64xx_plls {
|
|||
apll, mpll, epll,
|
||||
};
|
||||
|
||||
static void __iomem *reg_base;
|
||||
static bool is_s3c6400;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *s3c64xx_save_common;
|
||||
static struct samsung_clk_reg_dump *s3c64xx_save_soc;
|
||||
|
||||
/*
|
||||
* List of controller registers to be saved and restored during
|
||||
* a suspend/resume cycle.
|
||||
|
|
@ -87,6 +95,60 @@ static unsigned long s3c6410_clk_regs[] __initdata = {
|
|||
MEM0_GATE,
|
||||
};
|
||||
|
||||
static int s3c64xx_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, s3c64xx_save_common,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
|
||||
if (!is_s3c6400)
|
||||
samsung_clk_save(reg_base, s3c64xx_save_soc,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c64xx_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, s3c64xx_save_common,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
|
||||
if (!is_s3c6400)
|
||||
samsung_clk_restore(reg_base, s3c64xx_save_soc,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops s3c64xx_clk_syscore_ops = {
|
||||
.suspend = s3c64xx_clk_suspend,
|
||||
.resume = s3c64xx_clk_resume,
|
||||
};
|
||||
|
||||
static void s3c64xx_clk_sleep_init(void)
|
||||
{
|
||||
s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
if (!s3c64xx_save_common)
|
||||
goto err_warn;
|
||||
|
||||
if (!is_s3c6400) {
|
||||
s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
if (!s3c64xx_save_soc)
|
||||
goto err_soc;
|
||||
}
|
||||
|
||||
register_syscore_ops(&s3c64xx_clk_syscore_ops);
|
||||
return;
|
||||
|
||||
err_soc:
|
||||
kfree(s3c64xx_save_common);
|
||||
err_warn:
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
}
|
||||
#else
|
||||
static void s3c64xx_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* List of parent clocks common for all S3C64xx SoCs. */
|
||||
PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
|
||||
PNAME(uart_p) = { "mout_epll", "dout_mpll" };
|
||||
|
|
@ -391,11 +453,11 @@ static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f,
|
|||
|
||||
/* Register s3c64xx clocks. */
|
||||
void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
||||
unsigned long xusbxti_f, bool is_s3c6400,
|
||||
void __iomem *reg_base)
|
||||
unsigned long xusbxti_f, bool s3c6400,
|
||||
void __iomem *base)
|
||||
{
|
||||
unsigned long *soc_regs = NULL;
|
||||
unsigned long nr_soc_regs = 0;
|
||||
reg_base = base;
|
||||
is_s3c6400 = s3c6400;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
|
|
@ -403,13 +465,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
|||
panic("%s: failed to map registers\n", __func__);
|
||||
}
|
||||
|
||||
if (!is_s3c6400) {
|
||||
soc_regs = s3c6410_clk_regs;
|
||||
nr_soc_regs = ARRAY_SIZE(s3c6410_clk_regs);
|
||||
}
|
||||
|
||||
samsung_clk_init(np, reg_base, NR_CLKS, s3c64xx_clk_regs,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs), soc_regs, nr_soc_regs);
|
||||
samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
|
||||
/* Register external clocks. */
|
||||
if (!np)
|
||||
|
|
@ -452,6 +508,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
|||
|
||||
samsung_clk_register_alias(s3c64xx_clock_aliases,
|
||||
ARRAY_SIZE(s3c64xx_clock_aliases));
|
||||
s3c64xx_clk_sleep_init();
|
||||
|
||||
pr_info("%s clocks: apll = %lu, mpll = %lu\n"
|
||||
"\tepll = %lu, arm_clk = %lu\n",
|
||||
|
|
|
|||
|
|
@ -21,64 +21,45 @@ static void __iomem *reg_base;
|
|||
static struct clk_onecell_data clk_data;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *reg_dump;
|
||||
static unsigned long nr_reg_dump;
|
||||
|
||||
static int samsung_clk_suspend(void)
|
||||
void samsung_clk_save(void __iomem *base,
|
||||
struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
{
|
||||
struct samsung_clk_reg_dump *rd = reg_dump;
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < nr_reg_dump; i++, rd++)
|
||||
rd->value = __raw_readl(reg_base + rd->offset);
|
||||
|
||||
return 0;
|
||||
for (; num_regs > 0; --num_regs, ++rd)
|
||||
rd->value = readl(base + rd->offset);
|
||||
}
|
||||
|
||||
static void samsung_clk_resume(void)
|
||||
void samsung_clk_restore(void __iomem *base,
|
||||
const struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
{
|
||||
struct samsung_clk_reg_dump *rd = reg_dump;
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < nr_reg_dump; i++, rd++)
|
||||
__raw_writel(rd->value, reg_base + rd->offset);
|
||||
for (; num_regs > 0; --num_regs, ++rd)
|
||||
writel(rd->value, base + rd->offset);
|
||||
}
|
||||
|
||||
static struct syscore_ops samsung_clk_syscore_ops = {
|
||||
.suspend = samsung_clk_suspend,
|
||||
.resume = samsung_clk_resume,
|
||||
};
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump)
|
||||
{
|
||||
struct samsung_clk_reg_dump *rd;
|
||||
unsigned int i;
|
||||
|
||||
rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
|
||||
if (!rd)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < nr_rdump; ++i)
|
||||
rd[i].offset = rdump[i];
|
||||
|
||||
return rd;
|
||||
}
|
||||
|
||||
/* setup the essentials required to support clock lookup using ccf */
|
||||
void __init samsung_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks, unsigned long *rdump,
|
||||
unsigned long nr_rdump, unsigned long *soc_rdump,
|
||||
unsigned long nr_soc_rdump)
|
||||
unsigned long nr_clks)
|
||||
{
|
||||
reg_base = base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
if (rdump && nr_rdump) {
|
||||
unsigned int idx;
|
||||
reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
|
||||
* (nr_rdump + nr_soc_rdump), GFP_KERNEL);
|
||||
if (!reg_dump) {
|
||||
pr_err("%s: memory alloc for register dump failed\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (idx = 0; idx < nr_rdump; idx++)
|
||||
reg_dump[idx].offset = rdump[idx];
|
||||
for (idx = 0; idx < nr_soc_rdump; idx++)
|
||||
reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
|
||||
nr_reg_dump = nr_rdump + nr_soc_rdump;
|
||||
register_syscore_ops(&samsung_clk_syscore_ops);
|
||||
}
|
||||
#endif
|
||||
|
||||
clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
panic("could not allocate clock lookup table\n");
|
||||
|
|
|
|||
|
|
@ -313,9 +313,7 @@ struct samsung_pll_clock {
|
|||
_lock, _con, _rtable, _alias)
|
||||
|
||||
extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks, unsigned long *rdump,
|
||||
unsigned long nr_rdump, unsigned long *soc_rdump,
|
||||
unsigned long nr_soc_rdump);
|
||||
unsigned long nr_clks);
|
||||
extern void __init samsung_clk_of_register_fixed_ext(
|
||||
struct samsung_fixed_rate_clock *fixed_rate_clk,
|
||||
unsigned int nr_fixed_rate_clk,
|
||||
|
|
@ -340,4 +338,14 @@ extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
|
|||
|
||||
extern unsigned long _get_rate(const char *clk_name);
|
||||
|
||||
extern void samsung_clk_save(void __iomem *base,
|
||||
struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs);
|
||||
extern void samsung_clk_restore(void __iomem *base,
|
||||
const struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs);
|
||||
extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump);
|
||||
|
||||
#endif /* __SAMSUNG_CLK_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue