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[ARM] mv78xx0: enable eth2/eth3 on the mv78xx0 A0 development board 

The A0 revision of the mv78xx0 development board has four ethernet
ports, with PHY IDs 8-11, whereas the Z0 version has two, with PHY
addresses 8-9.  This patch configures the third and fourth ethernet
port to use the PHY addresses on the A0 board to enable use of those
ports -- if we are running on a Z0 board, the ge10/11 setup code in
common.c will force these back to PHYless mode.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
hifive-unleashed-5.1
Lennert Buytenhek 2009-02-20 02:32:30 +01:00 committed by Nicolas Pitre
parent 712424fd95
commit f1f5465782
1 changed files with 2 additions and 6 deletions
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8
arch/arm/mach-mv78xx0/db78x00-bp-setup.c
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@ -28,15 +28,11 @@ static struct mv643xx_eth_platform_data db78x00_ge01_data = {
};
static struct mv643xx_eth_platform_data db78x00_ge10_data = {
.phy_addr = MV643XX_ETH_PHY_NONE,
.speed = SPEED_1000,
.duplex = DUPLEX_FULL,
.phy_addr = MV643XX_ETH_PHY_ADDR(10),
};
static struct mv643xx_eth_platform_data db78x00_ge11_data = {
.phy_addr = MV643XX_ETH_PHY_NONE,
.speed = SPEED_1000,
.duplex = DUPLEX_FULL,
.phy_addr = MV643XX_ETH_PHY_ADDR(11),
};
static struct mv_sata_platform_data db78x00_sata_data = {