staging: comedi: s626: rename CamelCase variables
Rename the remaining CamelCase parameters and variables. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ian Abbott
Greg Kroah-Hartman
parent
19436a0dd7
commit
f1f7efce3b
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@ -145,7 +145,7 @@ struct enc_private {
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/*
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* Translation table to map IntSrc into equivalent RDMISC2 event flag bits.
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* static const uint16_t EventBits[][4] =
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* static const uint16_t event_bits[][4] =
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* { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) };
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*/
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@ -486,7 +486,7 @@ static void set_dac(struct comedi_device *dev, uint16_t chan, short dacdata)
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{
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struct s626_private *devpriv = dev->private;
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uint16_t signmask;
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uint32_t WSImage;
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uint32_t ws_image;
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uint32_t val;
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/*
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@ -516,11 +516,11 @@ static void set_dac(struct comedi_device *dev, uint16_t chan, short dacdata)
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*/
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/* Choose DAC chip select to be asserted */
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WSImage = (chan & 2) ? WS1 : WS2;
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ws_image = (chan & 2) ? WS1 : WS2;
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/* Slot 2: Transmit high data byte to target DAC */
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writel(XSD2 | XFIFO_1 | WSImage, devpriv->mmio + VECTPORT(2));
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writel(XSD2 | XFIFO_1 | ws_image, devpriv->mmio + VECTPORT(2));
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/* Slot 3: Transmit low data byte to target DAC */
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writel(XSD2 | XFIFO_0 | WSImage, devpriv->mmio + VECTPORT(3));
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writel(XSD2 | XFIFO_0 | ws_image, devpriv->mmio + VECTPORT(3));
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/* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
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writel(XSD2 | XFIFO_3 | WS3, devpriv->mmio + VECTPORT(4));
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/* Slot 5: running after writing target DAC's low data byte */
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@ -543,8 +543,8 @@ static void set_dac(struct comedi_device *dev, uint16_t chan, short dacdata)
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send_dac(dev, val);
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}
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static void write_trim_dac(struct comedi_device *dev, uint8_t LogicalChan,
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uint8_t DacData)
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static void write_trim_dac(struct comedi_device *dev, uint8_t logical_chan,
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uint8_t dac_data)
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{
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struct s626_private *devpriv = dev->private;
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uint32_t chan;
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@ -553,10 +553,10 @@ static void write_trim_dac(struct comedi_device *dev, uint8_t LogicalChan,
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* Save the new setpoint in case the application needs to read it back
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* later.
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*/
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devpriv->trim_setpoint[LogicalChan] = (uint8_t)DacData;
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devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
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/* Map logical channel number to physical channel number. */
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chan = trimchan[LogicalChan];
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chan = trimchan[logical_chan];
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/*
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* Set up TSL2 records for TrimDac write operation. All slots shift
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@ -586,7 +586,7 @@ static void write_trim_dac(struct comedi_device *dev, uint8_t LogicalChan,
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* Address the DAC channel within the trimdac device.
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* Include DAC setpoint data.
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*/
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send_dac(dev, (chan << 8) | DacData);
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send_dac(dev, (chan << 8) | dac_data);
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}
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static void load_trim_dacs(struct comedi_device *dev)
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@ -956,18 +956,18 @@ static irqreturn_t s626_irq_handler(int irq, void *d)
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static void reset_adc(struct comedi_device *dev, uint8_t *ppl)
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{
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struct s626_private *devpriv = dev->private;
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uint32_t *pRPS;
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uint32_t JmpAdrs;
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uint32_t *rps;
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uint32_t jmp_adrs;
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uint16_t i;
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uint16_t n;
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uint32_t LocalPPL;
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uint32_t local_ppl;
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struct comedi_cmd *cmd = &dev->subdevices->async->cmd;
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/* Stop RPS program in case it is currently running */
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s626_mc_disable(dev, MC1_ERPS1, P_MC1);
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/* Set starting logical address to write RPS commands. */
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pRPS = (uint32_t *)devpriv->rps_buf.logical_base;
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rps = (uint32_t *)devpriv->rps_buf.logical_base;
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/* Initialize RPS instruction pointer */
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writel((uint32_t)devpriv->rps_buf.physical_base,
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@ -976,8 +976,8 @@ static void reset_adc(struct comedi_device *dev, uint8_t *ppl)
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/* Construct RPS program in rps_buf DMA buffer */
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if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
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/* Wait for Start trigger. */
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*pRPS++ = RPS_PAUSE | RPS_SIGADC;
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*pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
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*rps++ = RPS_PAUSE | RPS_SIGADC;
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*rps++ = RPS_CLRSIGNAL | RPS_SIGADC;
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}
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/*
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@ -989,15 +989,15 @@ static void reset_adc(struct comedi_device *dev, uint8_t *ppl)
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* the previously programmed value.
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*/
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/* Write DEBI Write command and address to shadow RAM. */
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*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
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*pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
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*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
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*rps++ = RPS_LDREG | (P_DEBICMD >> 2);
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*rps++ = DEBI_CMD_WRWORD | LP_GSEL;
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*rps++ = RPS_LDREG | (P_DEBIAD >> 2);
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/* Write DEBI immediate data to shadow RAM: */
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*pRPS++ = GSEL_BIPOLAR5V; /* arbitrary immediate data value. */
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*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
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*rps++ = GSEL_BIPOLAR5V; /* arbitrary immediate data value. */
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*rps++ = RPS_CLRSIGNAL | RPS_DEBI;
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/* Reset "shadow RAM uploaded" flag. */
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*pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
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*pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
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*rps++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
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*rps++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
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/*
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* Digitize all slots in the poll list. This is implemented as a
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@ -1012,35 +1012,35 @@ static void reset_adc(struct comedi_device *dev, uint8_t *ppl)
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* (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
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* +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
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*/
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LocalPPL = (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
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GSEL_BIPOLAR10V);
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local_ppl = (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
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GSEL_BIPOLAR10V);
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/* Switch ADC analog gain. */
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/* Write DEBI command and address to shadow RAM. */
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*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
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*pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
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*rps++ = RPS_LDREG | (P_DEBICMD >> 2);
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*rps++ = DEBI_CMD_WRWORD | LP_GSEL;
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/* Write DEBI immediate data to shadow RAM. */
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*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
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*pRPS++ = LocalPPL;
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*rps++ = RPS_LDREG | (P_DEBIAD >> 2);
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*rps++ = local_ppl;
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/* Reset "shadow RAM uploaded" flag. */
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*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
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*rps++ = RPS_CLRSIGNAL | RPS_DEBI;
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/* Invoke shadow RAM upload. */
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*pRPS++ = RPS_UPLOAD | RPS_DEBI;
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*rps++ = RPS_UPLOAD | RPS_DEBI;
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/* Wait for shadow upload to finish. */
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*pRPS++ = RPS_PAUSE | RPS_DEBI;
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*rps++ = RPS_PAUSE | RPS_DEBI;
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/* Select ADC analog input channel. */
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*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
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*rps++ = RPS_LDREG | (P_DEBICMD >> 2);
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/* Write DEBI command and address to shadow RAM. */
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*pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
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*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
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*rps++ = DEBI_CMD_WRWORD | LP_ISEL;
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*rps++ = RPS_LDREG | (P_DEBIAD >> 2);
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/* Write DEBI immediate data to shadow RAM. */
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*pRPS++ = LocalPPL;
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*rps++ = local_ppl;
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/* Reset "shadow RAM uploaded" flag. */
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*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
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*rps++ = RPS_CLRSIGNAL | RPS_DEBI;
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/* Invoke shadow RAM upload. */
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*pRPS++ = RPS_UPLOAD | RPS_DEBI;
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*rps++ = RPS_UPLOAD | RPS_DEBI;
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/* Wait for shadow upload to finish. */
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*pRPS++ = RPS_PAUSE | RPS_DEBI;
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*rps++ = RPS_PAUSE | RPS_DEBI;
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/*
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* Delay at least 10 microseconds for analog input settling.
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@ -1049,42 +1049,42 @@ static void reset_adc(struct comedi_device *dev, uint8_t *ppl)
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* possible with NOPs because each RPS_JUMP flushes the RPS'
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* instruction prefetch pipeline.
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*/
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JmpAdrs =
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jmp_adrs =
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(uint32_t)devpriv->rps_buf.physical_base +
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(uint32_t)((unsigned long)pRPS -
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(uint32_t)((unsigned long)rps -
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(unsigned long)devpriv->
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rps_buf.logical_base);
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for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
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JmpAdrs += 8; /* Repeat to implement time delay: */
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*pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
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*pRPS++ = JmpAdrs;
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jmp_adrs += 8; /* Repeat to implement time delay: */
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*rps++ = RPS_JUMP; /* Jump to next RPS instruction. */
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*rps++ = jmp_adrs;
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}
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if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
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/* Wait for Start trigger. */
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*pRPS++ = RPS_PAUSE | RPS_SIGADC;
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*pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
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*rps++ = RPS_PAUSE | RPS_SIGADC;
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*rps++ = RPS_CLRSIGNAL | RPS_SIGADC;
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}
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/* Start ADC by pulsing GPIO1. */
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/* Begin ADC Start pulse. */
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*pRPS++ = RPS_LDREG | (P_GPIO >> 2);
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*pRPS++ = GPIO_BASE | GPIO1_LO;
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*pRPS++ = RPS_NOP;
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*rps++ = RPS_LDREG | (P_GPIO >> 2);
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*rps++ = GPIO_BASE | GPIO1_LO;
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*rps++ = RPS_NOP;
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/* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
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/* End ADC Start pulse. */
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*pRPS++ = RPS_LDREG | (P_GPIO >> 2);
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*pRPS++ = GPIO_BASE | GPIO1_HI;
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*rps++ = RPS_LDREG | (P_GPIO >> 2);
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*rps++ = GPIO_BASE | GPIO1_HI;
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/*
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* Wait for ADC to complete (GPIO2 is asserted high when ADC not
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* busy) and for data from previous conversion to shift into FB
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* BUFFER 1 register.
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*/
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*pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
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*rps++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
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/* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
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*pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
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*pRPS++ = (uint32_t)devpriv->ana_buf.physical_base +
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(devpriv->adc_items << 2);
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*rps++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
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*rps++ = (uint32_t)devpriv->ana_buf.physical_base +
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(devpriv->adc_items << 2);
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/*
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* If this slot's EndOfPollList flag is set, all channels have
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@ -1105,41 +1105,41 @@ static void reset_adc(struct comedi_device *dev, uint8_t *ppl)
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* is sometimes set to the previous conversion's data value.
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*/
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for (n = 0; n < (2 * RPSCLK_PER_US); n++)
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*pRPS++ = RPS_NOP;
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*rps++ = RPS_NOP;
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/*
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* Start a dummy conversion to cause the data from the last
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* conversion of interest to be shifted in.
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*/
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*pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
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*pRPS++ = GPIO_BASE | GPIO1_LO;
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*pRPS++ = RPS_NOP;
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*rps++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
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*rps++ = GPIO_BASE | GPIO1_LO;
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*rps++ = RPS_NOP;
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/* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
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*pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
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*pRPS++ = GPIO_BASE | GPIO1_HI;
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*rps++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
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*rps++ = GPIO_BASE | GPIO1_HI;
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/*
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* Wait for the data from the last conversion of interest to arrive
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* in FB BUFFER 1 register.
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*/
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*pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
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*rps++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
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/* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
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*pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
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*pRPS++ = (uint32_t)devpriv->ana_buf.physical_base +
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(devpriv->adc_items << 2);
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*rps++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
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*rps++ = (uint32_t)devpriv->ana_buf.physical_base +
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(devpriv->adc_items << 2);
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/* Indicate ADC scan loop is finished. */
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/* Signal ReadADC() that scan is done. */
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/* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC; */
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/* *rps++= RPS_CLRSIGNAL | RPS_SIGADC; */
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/* invoke interrupt */
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if (devpriv->ai_cmd_running == 1)
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*pRPS++ = RPS_IRQ;
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*rps++ = RPS_IRQ;
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/* Restart RPS program at its beginning. */
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*pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
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*pRPS++ = (uint32_t)devpriv->rps_buf.physical_base;
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*rps++ = RPS_JUMP; /* Branch to start of RPS program. */
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*rps++ = (uint32_t)devpriv->rps_buf.physical_base;
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/* End of RPS program build */
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}
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@ -1188,8 +1188,8 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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struct s626_private *devpriv = dev->private;
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uint16_t chan = CR_CHAN(insn->chanspec);
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uint16_t range = CR_RANGE(insn->chanspec);
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uint16_t AdcSpec = 0;
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uint32_t GpioImage;
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uint16_t adc_spec = 0;
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uint32_t gpio_image;
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int tmp;
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int n;
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@ -1198,29 +1198,29 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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* appropriate for register programming.
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*/
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if (range == 0)
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AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
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adc_spec = (chan << 8) | (GSEL_BIPOLAR5V);
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else
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AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
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adc_spec = (chan << 8) | (GSEL_BIPOLAR10V);
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/* Switch ADC analog gain. */
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debi_write(dev, LP_GSEL, AdcSpec); /* Set gain. */
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debi_write(dev, LP_GSEL, adc_spec); /* Set gain. */
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/* Select ADC analog input channel. */
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debi_write(dev, LP_ISEL, AdcSpec); /* Select channel. */
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debi_write(dev, LP_ISEL, adc_spec); /* Select channel. */
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for (n = 0; n < insn->n; n++) {
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/* Delay 10 microseconds for analog input settling. */
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udelay(10);
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/* Start ADC by pulsing GPIO1 low */
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GpioImage = readl(devpriv->mmio + P_GPIO);
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gpio_image = readl(devpriv->mmio + P_GPIO);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* and stretch it out */
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* Negate ADC Start command */
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writel(GpioImage | GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(gpio_image | GPIO1_HI, devpriv->mmio + P_GPIO);
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/*
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* Wait for ADC to complete (GPIO2 is asserted high when
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@ -1254,14 +1254,14 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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* Start a dummy conversion to cause the data from the
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* previous conversion to be shifted in.
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*/
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GpioImage = readl(devpriv->mmio + P_GPIO);
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gpio_image = readl(devpriv->mmio + P_GPIO);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* and stretch it out */
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
writel(gpio_image & ~GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
/* Negate ADC Start command */
|
||||
writel(GpioImage | GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
writel(gpio_image | GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
|
||||
/* Wait for the data to arrive in FB BUFFER 1 register. */
|
||||
|
||||
|
|
@ -1343,7 +1343,7 @@ static int s626_ns_to_timer(int *nanosec, int round_mode)
|
|||
static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
|
||||
int tick)
|
||||
{
|
||||
uint16_t Setup =
|
||||
uint16_t setup =
|
||||
(LOADSRC_INDX << BF_LOADSRC) | /* Preload upon index. */
|
||||
(INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
|
||||
(CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
|
||||
|
|
@ -1351,10 +1351,10 @@ static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
|
|||
(CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
|
||||
(CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
|
||||
(CLKENAB_INDEX << BF_CLKENAB);
|
||||
uint16_t valueSrclatch = LATCHSRC_A_INDXA;
|
||||
uint16_t value_latchsrc = LATCHSRC_A_INDXA;
|
||||
/* uint16_t enab = CLKENAB_ALWAYS; */
|
||||
|
||||
k->set_mode(dev, k, Setup, FALSE);
|
||||
k->set_mode(dev, k, setup, FALSE);
|
||||
|
||||
/* Set the preload register */
|
||||
preload(dev, k, tick);
|
||||
|
|
@ -1372,7 +1372,7 @@ static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
|
|||
/* set interrupt on overflow */
|
||||
k->set_int_src(dev, k, INTSRC_OVER);
|
||||
|
||||
set_latch_source(dev, k, valueSrclatch);
|
||||
set_latch_source(dev, k, value_latchsrc);
|
||||
/* k->set_enable(dev, k, (uint16_t)(enab != 0)); */
|
||||
}
|
||||
|
||||
|
|
@ -1729,25 +1729,25 @@ static int s626_enc_insn_config(struct comedi_device *dev,
|
|||
struct comedi_subdevice *s,
|
||||
struct comedi_insn *insn, unsigned int *data)
|
||||
{
|
||||
uint16_t Setup =
|
||||
uint16_t setup =
|
||||
(LOADSRC_INDX << BF_LOADSRC) | /* Preload upon index. */
|
||||
(INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
|
||||
(CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
|
||||
(CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
|
||||
(CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
|
||||
(CLKENAB_INDEX << BF_CLKENAB);
|
||||
/* uint16_t DisableIntSrc = TRUE; */
|
||||
/* uint16_t disable_int_src = TRUE; */
|
||||
/* uint32_t Preloadvalue; //Counter initial value */
|
||||
uint16_t valueSrclatch = LATCHSRC_AB_READ;
|
||||
uint16_t value_latchsrc = LATCHSRC_AB_READ;
|
||||
uint16_t enab = CLKENAB_ALWAYS;
|
||||
struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
|
||||
|
||||
/* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
|
||||
|
||||
k->set_mode(dev, k, Setup, TRUE);
|
||||
k->set_mode(dev, k, setup, TRUE);
|
||||
preload(dev, k, data[0]);
|
||||
k->pulse_index(dev, k);
|
||||
set_latch_source(dev, k, valueSrclatch);
|
||||
set_latch_source(dev, k, value_latchsrc);
|
||||
k->set_enable(dev, k, (enab != 0));
|
||||
|
||||
return insn->n;
|
||||
|
|
@ -1786,10 +1786,10 @@ static int s626_enc_insn_write(struct comedi_device *dev,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void write_misc2(struct comedi_device *dev, uint16_t NewImage)
|
||||
static void write_misc2(struct comedi_device *dev, uint16_t new_image)
|
||||
{
|
||||
debi_write(dev, LP_MISC1, MISC1_WENABLE); /* Enable writes to MISC2. */
|
||||
debi_write(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
|
||||
debi_write(dev, LP_WRMISC2, new_image); /* Write new image to MISC2. */
|
||||
debi_write(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2 */
|
||||
}
|
||||
|
||||
|
|
@ -1958,7 +1958,7 @@ static uint16_t get_mode_b(struct comedi_device *dev, struct enc_private *k)
|
|||
* ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
|
||||
*/
|
||||
static void set_mode_a(struct comedi_device *dev, struct enc_private *k,
|
||||
uint16_t setup, uint16_t DisableIntSrc)
|
||||
uint16_t setup, uint16_t disable_int_src)
|
||||
{
|
||||
struct s626_private *devpriv = dev->private;
|
||||
uint16_t cra;
|
||||
|
|
@ -1976,8 +1976,8 @@ static void set_mode_a(struct comedi_device *dev, struct enc_private *k,
|
|||
/* Clock enable is passed through. */
|
||||
crb |= (setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB);
|
||||
|
||||
/* Force IntSrc to Disabled if DisableIntSrc is asserted. */
|
||||
if (!DisableIntSrc)
|
||||
/* Force IntSrc to Disabled if disable_int_src is asserted. */
|
||||
if (!disable_int_src)
|
||||
cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
|
||||
CRABIT_INTSRC_A));
|
||||
|
||||
|
|
@ -2024,7 +2024,7 @@ static void set_mode_a(struct comedi_device *dev, struct enc_private *k,
|
|||
* If IntSrc has been forced to Disabled, update the MISC2 interrupt
|
||||
* enable mask to indicate the counter interrupt is disabled.
|
||||
*/
|
||||
if (DisableIntSrc)
|
||||
if (disable_int_src)
|
||||
devpriv->counter_int_enabs &= ~k->my_event_bits[3];
|
||||
|
||||
/*
|
||||
|
|
@ -2036,7 +2036,7 @@ static void set_mode_a(struct comedi_device *dev, struct enc_private *k,
|
|||
}
|
||||
|
||||
static void set_mode_b(struct comedi_device *dev, struct enc_private *k,
|
||||
uint16_t setup, uint16_t DisableIntSrc)
|
||||
uint16_t setup, uint16_t disable_int_src)
|
||||
{
|
||||
struct s626_private *devpriv = dev->private;
|
||||
uint16_t cra;
|
||||
|
|
@ -2054,8 +2054,8 @@ static void set_mode_b(struct comedi_device *dev, struct enc_private *k,
|
|||
/* Preload trigger source is passed through. */
|
||||
crb |= (setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B);
|
||||
|
||||
/* Force IntSrc to Disabled if DisableIntSrc is asserted. */
|
||||
if (!DisableIntSrc)
|
||||
/* Force IntSrc to Disabled if disable_int_src is asserted. */
|
||||
if (!disable_int_src)
|
||||
crb |= (setup & STDMSK_INTSRC) >>
|
||||
(STDBIT_INTSRC - CRBBIT_INTSRC_B);
|
||||
|
||||
|
|
@ -2110,7 +2110,7 @@ static void set_mode_b(struct comedi_device *dev, struct enc_private *k,
|
|||
* If IntSrc has been forced to Disabled, update the MISC2 interrupt
|
||||
* enable mask to indicate the counter interrupt is disabled.
|
||||
*/
|
||||
if (DisableIntSrc)
|
||||
if (disable_int_src)
|
||||
devpriv->counter_int_enabs &= ~k->my_event_bits[3];
|
||||
|
||||
/*
|
||||
|
|
@ -2163,17 +2163,17 @@ static uint16_t get_latch_source(struct comedi_device *dev,
|
|||
* 2=OverflowA (B counters only), 3=disabled.
|
||||
*/
|
||||
static void set_load_trig_a(struct comedi_device *dev, struct enc_private *k,
|
||||
uint16_t Trig)
|
||||
uint16_t trig)
|
||||
{
|
||||
debi_replace(dev, k->my_cra, ~CRAMSK_LOADSRC_A,
|
||||
Trig << CRABIT_LOADSRC_A);
|
||||
trig << CRABIT_LOADSRC_A);
|
||||
}
|
||||
|
||||
static void set_load_trig_b(struct comedi_device *dev, struct enc_private *k,
|
||||
uint16_t Trig)
|
||||
uint16_t trig)
|
||||
{
|
||||
debi_replace(dev, k->my_crb, ~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL),
|
||||
Trig << CRBBIT_LOADSRC_B);
|
||||
trig << CRBBIT_LOADSRC_B);
|
||||
}
|
||||
|
||||
static uint16_t get_load_trig_a(struct comedi_device *dev,
|
||||
|
|
@ -2190,11 +2190,11 @@ static uint16_t get_load_trig_b(struct comedi_device *dev,
|
|||
|
||||
/*
|
||||
* Return/set counter interrupt source and clear any captured
|
||||
* index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
|
||||
* index/overflow events. int_source: 0=Disabled, 1=OverflowOnly,
|
||||
* 2=IndexOnly, 3=IndexAndOverflow.
|
||||
*/
|
||||
static void set_int_src_a(struct comedi_device *dev, struct enc_private *k,
|
||||
uint16_t IntSource)
|
||||
uint16_t int_source)
|
||||
{
|
||||
struct s626_private *devpriv = dev->private;
|
||||
|
||||
|
|
@ -2204,16 +2204,16 @@ static void set_int_src_a(struct comedi_device *dev, struct enc_private *k,
|
|||
|
||||
/* Program counter interrupt source. */
|
||||
debi_replace(dev, k->my_cra, ~CRAMSK_INTSRC_A,
|
||||
IntSource << CRABIT_INTSRC_A);
|
||||
int_source << CRABIT_INTSRC_A);
|
||||
|
||||
/* Update MISC2 interrupt enable mask. */
|
||||
devpriv->counter_int_enabs =
|
||||
(devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
|
||||
k->my_event_bits[IntSource];
|
||||
k->my_event_bits[int_source];
|
||||
}
|
||||
|
||||
static void set_int_src_b(struct comedi_device *dev, struct enc_private *k,
|
||||
uint16_t IntSource)
|
||||
uint16_t int_source)
|
||||
{
|
||||
struct s626_private *devpriv = dev->private;
|
||||
uint16_t crb;
|
||||
|
|
@ -2228,12 +2228,12 @@ static void set_int_src_b(struct comedi_device *dev, struct enc_private *k,
|
|||
/* Program counter interrupt source. */
|
||||
debi_write(dev, k->my_crb,
|
||||
(uint16_t)((crb & ~CRBMSK_INTSRC_B) |
|
||||
(IntSource << CRBBIT_INTSRC_B)));
|
||||
(int_source << CRBBIT_INTSRC_B)));
|
||||
|
||||
/* Update MISC2 interrupt enable mask. */
|
||||
devpriv->counter_int_enabs =
|
||||
(devpriv->counter_int_enabs & ~k->my_event_bits[3]) |
|
||||
k->my_event_bits[IntSource];
|
||||
k->my_event_bits[int_source];
|
||||
}
|
||||
|
||||
static uint16_t get_int_src_a(struct comedi_device *dev, struct enc_private *k)
|
||||
|
|
@ -2444,7 +2444,7 @@ static void counters_init(struct comedi_device *dev)
|
|||
{
|
||||
int chan;
|
||||
struct enc_private *k;
|
||||
uint16_t Setup =
|
||||
uint16_t setup =
|
||||
(LOADSRC_INDX << BF_LOADSRC) | /* Preload upon index. */
|
||||
(INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
|
||||
(CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
|
||||
|
|
@ -2458,7 +2458,7 @@ static void counters_init(struct comedi_device *dev)
|
|||
*/
|
||||
for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
|
||||
k = &encpriv[chan];
|
||||
k->set_mode(dev, k, Setup, TRUE);
|
||||
k->set_mode(dev, k, setup, TRUE);
|
||||
k->set_int_src(dev, k, 0);
|
||||
k->reset_cap_flags(dev, k);
|
||||
k->set_enable(dev, k, CLKENAB_ALWAYS);
|
||||
|
|
@ -2490,7 +2490,7 @@ static int s626_allocate_dma_buffers(struct comedi_device *dev)
|
|||
static void s626_initialize(struct comedi_device *dev)
|
||||
{
|
||||
struct s626_private *devpriv = dev->private;
|
||||
dma_addr_t pPhysBuf;
|
||||
dma_addr_t phys_buf;
|
||||
uint16_t chan;
|
||||
int i;
|
||||
|
||||
|
|
@ -2580,19 +2580,19 @@ static void s626_initialize(struct comedi_device *dev)
|
|||
* a defined state after a PCI reset.
|
||||
*/
|
||||
{
|
||||
uint8_t PollList;
|
||||
uint16_t AdcData;
|
||||
uint16_t StartVal;
|
||||
uint8_t poll_list;
|
||||
uint16_t adc_data;
|
||||
uint16_t start_val;
|
||||
uint16_t index;
|
||||
unsigned int data[16];
|
||||
|
||||
/* Create a simple polling list for analog input channel 0 */
|
||||
PollList = EOPL;
|
||||
reset_adc(dev, &PollList);
|
||||
poll_list = EOPL;
|
||||
reset_adc(dev, &poll_list);
|
||||
|
||||
/* Get initial ADC value */
|
||||
s626_ai_rinsn(dev, dev->subdevices, NULL, data);
|
||||
StartVal = data[0];
|
||||
start_val = data[0];
|
||||
|
||||
/*
|
||||
* VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
|
||||
|
|
@ -2606,8 +2606,8 @@ static void s626_initialize(struct comedi_device *dev)
|
|||
*/
|
||||
for (index = 0; index < 500; index++) {
|
||||
s626_ai_rinsn(dev, dev->subdevices, NULL, data);
|
||||
AdcData = data[0];
|
||||
if (AdcData != StartVal)
|
||||
adc_data = data[0];
|
||||
if (adc_data != start_val)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -2630,10 +2630,10 @@ static void s626_initialize(struct comedi_device *dev)
|
|||
* single DWORD will be transferred each time a DMA transfer is
|
||||
* enabled.
|
||||
*/
|
||||
pPhysBuf = devpriv->ana_buf.physical_base +
|
||||
phys_buf = devpriv->ana_buf.physical_base +
|
||||
(DAC_WDMABUF_OS * sizeof(uint32_t));
|
||||
writel((uint32_t)pPhysBuf, devpriv->mmio + P_BASEA2_OUT);
|
||||
writel((uint32_t)(pPhysBuf + sizeof(uint32_t)),
|
||||
writel((uint32_t)phys_buf, devpriv->mmio + P_BASEA2_OUT);
|
||||
writel((uint32_t)(phys_buf + sizeof(uint32_t)),
|
||||
devpriv->mmio + P_PROTA2_OUT);
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue