drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY
Currently the DSI PHY timings are hard-coded for a specific panel for the 10nm PHY. Replace this with the auto PHY timing calculator which can calculate the PHY timings for any panel. Changes in v4: - None Changes in v3: - None Changes in v2: - None Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -265,6 +265,115 @@ int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
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return 0;
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}
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int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req)
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{
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const unsigned long bit_rate = clk_req->bitclk_rate;
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const unsigned long esc_rate = clk_req->escclk_rate;
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s32 ui, ui_x8, lpx;
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s32 tmax, tmin;
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s32 pcnt0 = 50;
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s32 pcnt1 = 50;
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s32 pcnt2 = 10;
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s32 pcnt3 = 30;
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s32 pcnt4 = 10;
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s32 pcnt5 = 2;
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s32 coeff = 1000; /* Precision, should avoid overflow */
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s32 hb_en, hb_en_ckln;
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s32 temp;
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if (!bit_rate || !esc_rate)
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return -EINVAL;
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timing->hs_halfbyte_en = 0;
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hb_en = 0;
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timing->hs_halfbyte_en_ckln = 0;
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hb_en_ckln = 0;
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ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
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ui_x8 = ui << 3;
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lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
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temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
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tmin = max_t(s32, temp, 0);
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temp = (95 * coeff) / ui_x8;
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tmax = max_t(s32, temp, 0);
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timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
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temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
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tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = (tmin > 255) ? 511 : 255;
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timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
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tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
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temp = 105 * coeff + 12 * ui - 20 * coeff;
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tmax = (temp + 3 * ui) / ui_x8;
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timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
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temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
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tmin = max_t(s32, temp, 0);
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temp = (85 * coeff + 6 * ui) / ui_x8;
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tmax = max_t(s32, temp, 0);
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timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
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temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
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tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = 255;
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timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
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tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
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temp = 105 * coeff + 12 * ui - 20 * coeff;
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tmax = (temp / ui_x8) - 1;
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timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
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temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
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timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
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tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
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tmax = 255;
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timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
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temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
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timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
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temp = 60 * coeff + 52 * ui - 43 * ui;
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tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = 63;
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timing->shared_timings.clk_post =
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linear_inter(tmax, tmin, pcnt2, 0, false);
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temp = 8 * ui + (timing->clk_prepare << 3) * ui;
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temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
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temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
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(((timing->hs_rqst_ckln << 3) + 8) * ui);
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tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
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tmax = 63;
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if (tmin > tmax) {
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temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
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timing->shared_timings.clk_pre = temp >> 1;
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timing->shared_timings.clk_pre_inc_by_2 = 1;
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} else {
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timing->shared_timings.clk_pre =
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linear_inter(tmax, tmin, pcnt2, 0, false);
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timing->shared_timings.clk_pre_inc_by_2 = 0;
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}
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timing->ta_go = 3;
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timing->ta_sure = 0;
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timing->ta_get = 4;
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DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
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timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
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timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
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timing->clk_trail, timing->clk_prepare, timing->hs_exit,
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timing->hs_zero, timing->hs_prepare, timing->hs_trail,
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timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
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timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
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timing->hs_prep_dly_ckln);
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return 0;
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}
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask)
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{
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@ -101,6 +101,8 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask);
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int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
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@ -79,34 +79,6 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
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}
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static int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req)
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{
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/*
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* TODO: These params need to be computed, they're currently hardcoded
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* for a 1440x2560@60Hz panel with a byteclk of 100.618 Mhz, and a
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* default escape clock of 19.2 Mhz.
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*/
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timing->hs_halfbyte_en = 0;
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timing->clk_zero = 0x1c;
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timing->clk_prepare = 0x07;
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timing->clk_trail = 0x07;
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timing->hs_exit = 0x23;
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timing->hs_zero = 0x21;
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timing->hs_prepare = 0x07;
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timing->hs_trail = 0x07;
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timing->hs_rqst = 0x05;
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timing->ta_sure = 0x00;
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timing->ta_go = 0x03;
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timing->ta_get = 0x04;
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timing->shared_timings.clk_pre = 0x2d;
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timing->shared_timings.clk_post = 0x0d;
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return 0;
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}
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static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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struct msm_dsi_phy_clk_request *clk_req)
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{
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